PIC24HJ12GP201 Datasheet, PDF(41/234 Page) Microchip Technology – High-Performance, 16-Bit Microcontrollers

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PIC24HJ12GP201 Datasheet, PDF (41/234 Pages) Microchip Technology – High-Performance, 16-Bit Microcontrollers

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PIC24HJ12GP201/202

REGISTER 4-1: NVMCON: FLASH MEMORY CONTROL REGISTER

R/SO-0(1)

R/W-0(1)

R/W-0(1)

U-0

U-0

U-0

U-0

WR

WREN

WRERR

â

â

â

â

bit 15

U-0

R/W-0(1)

U-0

â

ERASE

â

bit 7

U-0

R/W-0(1)

R/W-0(1)

R/W-0(1)

â

NVMOP<3:0>(2)

U-0

â

bit 8

R/W-0(1)

bit 0

Legend:

R = Readable bit

-n = Value at POR

SO = Satiable only bit

W = Writable bit

â1â = Bit is set

U = Unimplemented bit, read as â0â

â0â = Bit is cleared

x = Bit is unknown

bit 15

bit 14

bit 13

bit 12-7

bit 6

bit 5-4

bit 3-0

WR: Write Control bit

1 = Initiates a Flash memory program or erase operation. The operation is self-timed and the bit is

cleared by hardware once operation is complete.

0 = Program or erase operation is complete and inactive

WREN: Write Enable bit

1 = Enable Flash program/erase operations

0 = Inhibit Flash program/erase operations

WRERR: Write Sequence Error Flag bit

1 = An improper program or erase sequence attempt or termination has occurred (bit is set

automatically on any set attempt of the WR bit)

0 = The program or erase operation completed normally

Unimplemented: Read as â0â

ERASE: Erase/Program Enable bit

1 = Perform the erase operation specified by NVMOP<3:0> on the next WR command

0 = Perform the program operation specified by NVMOP<3:0> on the next WR command

Unimplemented: Read as â0â

NVMOP<3:0>: NVM Operation Select bits(2)

If ERASE = 1:

1111 = Memory bulk erase operation

1101 = Erase General Segment

1100 = Erase Secure Segment

0011 = No operation

0010 = Memory page erase operation

0001 = No operation

0000 = Erase a single Configuration register byte

If ERASE = 0:

1111 = No operation

1101 = No operation

1100 = No operation

0011 = Memory word program operation

0010 = No operation

0001 = Memory row program operation

0000 = Program a single Configuration register byte

Note 1: These bits can only be Reset on POR.

2: All other combinations of NVMOP<3:0> are unimplemented.

Â© 2007 Microchip Technology Inc.

Preliminary

DS70282B-page 39

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