PIC24HJ12GP201 Datasheet, PDF (167/234 Pages) Microchip Technology – High-Performance, 16-Bit Microcontrollers

PIC24HJ12GP201/202
TABLE 18-2: PIC24HJ12GP201/202 CONFIGURATION BITS DESCRIPTION (CONTINUED)
Bit Field
Register
Description
FWDTEN
FWDT
Watchdog Timer Enable bit
1 = Watchdog Timer always enabled (LPRC oscillator cannot be disabled.
Clearing the SWDTEN bit in the RCON register will have no effect.)
0 = Watchdog Timer enabled/disabled by user software (LPRC can be
disabled by clearing the SWDTEN bit in the RCON register)
WINDIS
WDTPRE
WDTPOST<3:0>
ALTI2C
FPWRT<2:0>
FWDT
FWDT
FWDT
FPOR
FPOR
Watchdog Timer Window Enable bit
1 = Watchdog Timer in Non-Window mode
0 = Watchdog Timer in Window mode
Watchdog Timer Prescaler bit
1 = 1:128
0 = 1:32
Watchdog Timer Postscaler bits
1111 = 1:32,768
1110 = 1:16,384
.
.
.
0001 = 1:2
0000 = 1:1
Alternate I²C™ pins
1 = I²C mapped to SDA1/SCL1 pins
0 = I²C mapped to ASDA1/ASCL1 pins
Power-on Reset Timer Value Select bits
111 = PWRT = 128 ms
110 = PWRT = 64 ms
101 = PWRT = 32 ms
100 = PWRT = 16 ms
011 = PWRT = 8 ms
010 = PWRT = 4 ms
001 = PWRT = 2 ms
000 = PWRT = Disabled
© 2007 Microchip Technology Inc.
Preliminary
DS70282B-page 165