PIC24HJ12GP201 Datasheet, PDF (20/234 Pages) Microchip Technology – High-Performance, 16-Bit Microcontrollers

PIC24HJ12GP201/202
3.1.1
PROGRAM MEMORY
ORGANIZATION
The program memory space is organized in word-
addressable blocks. Although it is treated as 24 bits
wide, it is more appropriate to think of each address of
the program memory as a lower and upper word, with
the upper byte of the upper word being unimplemented.
The lower word always has an even address, while the
upper word has an odd address (Figure 3-2).
Program memory addresses are always word-aligned
on the lower word, and addresses are incremented or
decremented by two during code execution. This
arrangement provides compatibility with data memory
space addressing and makes data in the program
memory space accessible.
3.1.2 INTERRUPT AND TRAP VECTORS
All PIC24HJ12GP201/202 devices reserve the
addresses between 0x00000 and 0x000200 for hard-
coded program execution vectors. A hardware Reset
vector is provided to redirect code execution from the
default value of the PC on device Reset to the actual
start of code. A GOTO instruction is programmed by the
user application at 0x000000, with the actual address
for the start of code at 0x000002.
PIC24HJ12GP201/202 devices also have two interrupt
vector tables, located from 0x000004 to 0x0000FF and
0x000100 to 0x0001FF. These vector tables allow each
of the many device interrupt sources to be handled by
separate Interrupt Service Routines (ISRs). A more
detailed discussion of the interrupt vector tables is
provided in Section 6.1 “Interrupt Vector Table”.
FIGURE 3-2:
PROGRAM MEMORY ORGANIZATION
msw
Address
0x000001
0x000003
0x000005
0x000007
most significant word
23
16
00000000
00000000
00000000
00000000
least significant word
8
Program Memory
‘Phantom’ Byte
(read as ‘0’)
Instruction Width
PC Address
(lsw Address)
0
0x000000
0x000002
0x000004
0x000006
DS70282B-page 18
Preliminary
© 2007 Microchip Technology Inc.