PIC24HJ12GP201 Datasheet, PDF (135/234 Pages) Microchip Technology – High-Performance, 16-Bit Microcontrollers

PIC24HJ12GP201/202
15.0 INTER-INTEGRATED CIRCUIT
(I²C)
Note:
This data sheet summarizes the features
of the PIC24HJ12GP201/202 devices. It is
not intended to be a comprehensive
reference source. To complement the
information in this data sheet, refer to the
“PIC24H Family Reference Manual”.
Please see the Microchip web site
(www.microchip.com) for the latest
PIC24H Family Reference Manual
chapters.
The Inter-Integrated Circuit (I²C) module provides
complete hardware support for both Slave and Multi-
Master modes of the I²C serial communication
standard, with a 16-bit interface.
The I²C module has a 2-pin interface:
• The SCLx pin is clock
• The SDAx pin is data
The I²C module offers the following key features:
• I²C interface supporting both Master and Slave
modes of operation
• I²C Slave mode supports 7 and 10-bit address
• I²C Master mode supports 7 and 10-bit address
• I²C port allows bidirectional transfers between
master and slaves
• Serial clock synchronization for I²C port can be
used as a handshake mechanism to suspend and
resume serial transfer (SCLREL control)
• I²C supports multi-master operation, detects bus
collision and arbitrates accordingly
15.1 Operating Modes
The hardware fully implements all the master and slave
functions of the I²C Standard and Fast mode
specifications, as well as 7 and 10-bit addressing.
The I²C module can operate either as a slave or a
master on an I²C bus.
The following types of I²C operation are supported:
• I²C slave operation with 7-bit address
• I²C slave operation with 10-bit address
• I²C master operation with 7 or 10-bit address
For details about the communication sequence in each
of these modes, refer to the “PIC24H Family Reference
Manual”. Please see the Microchip web site
(www.microchip.com) for the latest PIC24H Family
Reference Manual chapters.
15.2 I²C Registers
I2CxCON and I2CxSTAT are control and status
registers, respectively. The I2CxCON register is
readable and writable. The lower six bits of I2CxSTAT
are read-only. The remaining bits of the I2CSTAT are
read/write.
• I2CxRSR is the shift register used for shifting data
• I2CxRCV is the receive buffer and the register to
which data bytes are written, or from which data
bytes are read
• I2CxTRN is the transmit register to which bytes
are written during a transmit operation
• The I2CxADD register holds the slave address
• A status bit, ADD10, indicates 10-bit Address
mode
• I2CxBRG acts as the Baud Rate Generator
(BRG) reload value
In receive operations, I2CxRSR and I2CxRCV together
form a double-buffered receiver. When I2CxRSR
receives a complete byte, it is transferred to I2CxRCV,
and an interrupt pulse is generated.
15.3 I²C Interrupts
The I²C module generates two interrupt flags:
• MI2CxIF (I²C Master Events Interrupt flag)
• SI2CxIF (I²C Slave Events Interrupt flag).
A separate interrupt is generated for all I²C error
conditions.
15.4 Baud Rate Generator
In I²C Master mode, the reload value for the Baud Rate
Generator (BRG) is located in the I2CxBRG register.
When the BRG is loaded with this value, the BRG
counts down to zero and stops until another reload has
taken place. If clock arbitration is taking place, for
example, the BRG is reloaded when the SCLx pin is
sampled high.
As per the I²C standard, FSCL can be 100 kHz or
400 kHz. However, the user application can specify any
baud rate up to 1 MHz. I2CxBRG values of ‘0’ or ‘1’ are
illegal.
EQUATION 15-1: SERIAL CLOCK RATE
( ) I2CxBRG =
FCY
FSCL
–
FCY
10,000,000
–1
© 2007 Microchip Technology Inc.
Preliminary
DS70282B-page 133