PIC24HJ12GP201 Datasheet, PDF (19/234 Pages) Microchip Technology – High-Performance, 16-Bit Microcontrollers

PIC24HJ12GP201/202
3.0 MEMORY ORGANIZATION
Note:
This data sheet summarizes the features
of the PIC24HJ12GP201/202 devices. It is
not intended to be a comprehensive
reference source. To complement the
information in this data sheet, refer to the
“PIC24H Family Reference Manual”.
Please see the Microchip web site
(www.microchip.com) for the latest
PIC24H Family Reference Manual
chapters.
The PIC24HJ12GP201/202 architecture features
separate program and data memory spaces and
buses. This architecture also allows the direct access
of program memory from the data space during code
execution.
3.1 Program Address Space
The program address memory space of the
PIC24HJ12GP201/202 devices is 4M instructions. The
space is addressable by a 24-bit value derived either
from the 23-bit Program Counter (PC) during program
execution, or from table operation or data space
remapping as described in Section 3.4 “Interfacing
Program and Data Memory Spaces”.
User application access to the program memory space is
restricted to the lower half of the address range (0x000000
to 0x7FFFFF). The exception is the use of TBLRD/TBLWT
operations, which use TBLPAG<7> to permit access to the
Configuration bits and Device ID sections of the
configuration memory space.
The memory map for the PIC24HJ12GP201/202 device is
shown in Figure 3-1.
FIGURE 3-1:
PROGRAM MEMORY FOR PIC24HJ12GP201/202 DEVICES
PIC24HJ12GP201/202
GOTO Instruction
Reset Address
Interrupt Vector Table
Reserved
Alternate Vector Table
User Program
Flash Memory
(4K instructions)
0x000000
0x000002
0x000004
0x0000FE
0x000100
0x000104
0x0001FE
0x000200
0x001FFE
0x002000
© 2007 Microchip Technology Inc.
Unimplemented
(Read ‘0’s)
0x7FFFFE
0x800000
Reserved
Device Configuration
Registers
0xF7FFFE
0xF80000
0xF80017
0xF80018
Reserved
DEVID (2)
0xFEFFFE
0xFF0000
0xFFFFFE
Preliminary
DS70282B-page 17