PIC24HJ12GP201 Datasheet, PDF (47/234 Pages) Microchip Technology – High-Performance, 16-Bit Microcontrollers

PIC24HJ12GP201/202
REGISTER 5-1: RCON: RESET CONTROL REGISTER⁽¹⁾
bit 1
bit 0
Note 1:
2:
BOR: Brown-out Reset Flag bit
1 = A Brown-out Reset has occurred
0 = A Brown-out Reset has not occurred
POR: Power-on Reset Flag bit
1 = A Power-up Reset has occurred
0 = A Power-up Reset has not occurred
All of the Reset status bits can be set or cleared in software. Setting one of these bits in software does not
cause a device Reset.
If the FWDTEN Configuration bit is ‘1’ (unprogrammed), the WDT is always enabled, regardless of the
SWDTEN bit setting.
TABLE 5-1: RESET FLAG BIT OPERATION⁽¹⁾
Flag Bit
Setting Event
TRAPR (RCON<15>)
IOPUWR (RCON<14>)
CM (RCON<9>)
EXTR (RCON<7>)
SWR (RCON<6>)
WDTO (RCON<4>)
Trap conflict event
Illegal opcode or uninitialized
W register access
Configuration mismatch
MCLR Reset
RESET instruction
WDT time-out
SLEEP (RCON<3>)
PWRSAV #SLEEP instruction
IDLE (RCON<2>)
PWRSAV #IDLE instruction
BOR (RCON<1>)
BOR
POR (RCON<0>)
POR
Note 1: All Reset flag bits may be set or cleared by the user software.
Clearing Event
POR, BOR
POR, BOR
POR, BOR
POR
POR, BOR
PWRSAV instruction, POR, BOR,
CLRWDT instruction
POR, BOR
POR, BOR
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© 2007 Microchip Technology Inc.
Preliminary
DS70282B-page 45