PIC24HJ12GP201 Datasheet, PDF (129/234 Pages) Microchip Technology – High-Performance, 16-Bit Microcontrollers

PIC24HJ12GP201/202
FIGURE 14-2:
SPI MASTER/SLAVE CONNECTION
PROCESSOR 1 (SPI Master)
PROCESSOR 2 (SPI Slave)
SDOx
Serial Receive Buffer
(SPIxRXB)
SDIx
Serial Receive Buffer
(SPIxRXB)
Shift Register
(SPIxSR)
MSb
LSb
SDIx
SDOx
Shift Register
(SPIxSR)
MSb
LSb
Serial Transmit Buffer
(SPIxTXB)
Serial Transmit Buffer
(SPIxTXB)
SPI Buffer
(SPIxBUF)⁽²⁾
SCKx ^{Serial Clock}
SCKx
SSx⁽¹⁾
SPI Buffer
(SPIxBUF)⁽²⁾
(MSTEN (SPIxCON1<5>) = 1)
(SSEN (SPIxCON1<7>) = 1 and MSTEN (SPIxCON1<5>) = 0)
Note 1: Using the SSx pin in Slave mode of operation is optional.
2: User application must write transmit data to read received data from SPIxBUF. The SPIxTXB and SPIxRXB registers
are memory mapped to SPIxBUF.
FIGURE 14-3:
SPI MASTER, FRAME MASTER CONNECTION DIAGRAM
PIC24H
PROCESSOR 2
SDOx
SDIx
SDIx
Serial Clock
SCKx
SSx
Frame Sync
Pulse
SDOx
SCKx
SSx
FIGURE 14-4:
SPI MASTER, FRAME SLAVE CONNECTION DIAGRAM
PIC24H
PROCESSOR 2
SDOx
SDIx
SCKx
Serial Clock
SSx
Frame Sync
Pulse
SDIx
SDOx
SCKx
SSx
© 2007 Microchip Technology Inc.
Preliminary
DS70282B-page 127