PIC32MX320F032H_11 Datasheet, PDF(82/214 Page) Microchip Technology – High-Performance, General Purpose and USB, 32-bit Flash Microcontrollers

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PIC32MX320F032H_11 Datasheet, PDF (82/214 Pages) Microchip Technology – High-Performance, General Purpose and USB, 32-bit Flash Microcontrollers

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TABLE 4-43: USB REGISTERS MAP(1)

Bits

31/15 30/14 29/13 28/12 27/11 26/10 25/9

24/8

23/7

22/6

21/5

20/4

19/3

18/2

17/1

16/0

5040

U1OTG

IR(2)

31:16

15:0

IDIF T1MSECIF LSTATEIF ACTVIF SESVDIF SESENDIF

VBUSVDIF 0000

5050

U1OTG

31:16

15:0

â 0000

IDIE T1MSECIE LSTATEIE ACTVIE SESVDIE SESENDIE

VBUSVDIE 0000

5060

U1OTG

STAT(3)

31:16

15:0

â 0000

LSTATE

SESVD SESEND

VBUSVD 0000

5070

U1OTG

CON

31:16

15:0

â 0000

DPPULUP DMPULUP DPPULDWN DMPULDWN VBUSON OTGEN VBUSCHG VBUSDIS 0000

31:16 â

5080 U1PWRC

15:0

UACTPND(4)

USLPGRD

â 0000

â USUSPEND USBPWR 0000

31:16 â

â 0000

5200 U1IR(2)

URSTIF 0000

15:0

STALLIF ATTACHIF RESUMEIF IDLEIF

TRNIF SOFIF UERRIF

DETACHIF 0000

31:16 â

â 0000

5210 U1IE

URSTIE 0000

15:0

STALLIE ATTACHIE RESUMEIE IDLEIE

TRNIE SOFIE UERRIE

DETACHIE 0000

31:16 â

â 0000

5220 U1EIR

CRC5EF

0000

15:0

BTSEF BMXEF DMAEF

BTOEF DFN8EF CRC16EF

PIDEF

EOFEF

0000

31:16 â

â 0000

5230 U1EIE

CRC5EE

0000

15:0

BTSEE BMXEE DMAEE

BTOEE DFN8EE CRC16EE

PIDEE

EOFEE

0000

5240 U1STAT(3) 31:16

15:0

ENDPT<3:0>(4)

DIR

PPBI

â 0000

31:16 â

â 0000

5250 U1CON

15:0

JSTATE(4) SE0(4)

PKTDIS

USBEN 0000

USBRST HOSTEN RESUME PPBRST

TOKBUSY

SOFEN 0000

31:16 â

5260 U1ADDR

15:0

LSPDEN

â 0000

DEVADDR<6:0>

0000

31:16 â

â 0000

5270 U1BDTP1

15:0

BDTPTRL<7:1>

â 0000

Legend:

Note 1:

x = unknown value on Reset, â = unimplemented, read as â0â. Reset values are shown in hexadecimal.

Except where noted, all registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 âCLR, SET and INV

Registersâ for more information.

2: This register does not have associated CLR, SET, and INV registers.

3: All bits in this register are read-only; therefore, CLR, SET, and INV registers are not supported.

4: The reset value for this bit is undefined.

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