PIC32MX320F032H_11 Datasheet, PDF (144/214 Pages) Microchip Technology – High-Performance, General Purpose and USB, 32-bit Flash Microcontrollers

PIC32MX3XX/4XX
TABLE 27-1:
Instruction
RDPGPR
ROTR
ROTRV
SB
SC
MIPS32^® INSTRUCTION SET (CONTINUED)
Description
Read GPR from Previous Shadow Set
Rotate Word Right
Rotate Word Right Variable
Store Byte
Store Conditional Word
SDBBP
SEB
SEH
SH
SLL
SLLV
SLT
Software Debug Break Point
Sign-Extend Byte
Sign-Extend Half
Store Half
Shift Left Logical
Shift Left Logical Variable
Set on Less Than
SLTI
Set on Less Than Immediate
SLTIU
Set on Less Than Immediate Unsigned
SLTU
Set on Less Than Unsigned
SRA
SRAV
SRL
SRLV
SSNOP
SUB
SUBU
SW
SWL
SWR
SYNC
Shift Right Arithmetic
Shift Right Arithmetic Variable
Shift Right Logical
Shift Right Logical Variable
Superscalar Inhibit No Operation
Integer Subtract
Unsigned Subtract
Store Word
Store Word Left
Store Word Right
Synchronize
SYSCALL
TEQ
System Call
Trap if Equal
TEQI
Trap if Equal Immediate
Note 1: This instruction is deprecated and should not be used.
Function
Rt = SGPR[SRSCtl_PSS, Rd]
Rd = Rt_sa-1..0 || Rt_31..sa
Rd = Rt_Rs-1..0 || Rt_31..Rs
(byte)Mem[Rs+offset] = Rt
if LL_bit = 1
mem[Rs+offset> = Rt
Rt = LL_bit
Trap to SW Debug Handler
Rd = SignExtend (Rs-7...0)
Rd = SignExtend (Rs-15...0)
(half)Mem[Rs+offset> = Rt
Rd = Rt << sa
Rd = Rt << Rs[4:0]
if (int)Rs < (int)Rt
Rd = 1
else
Rd = 0
if (int)Rs < (int)Immed
Rt = 1
else
Rt = 0
if (uns)Rs < (uns)Immed
Rt = 1
else
Rt = 0
if (uns)Rs < (uns)Immed
Rd = 1
else
Rd = 0
Rd = (int)Rt >> sa
Rd = (int)Rt >> Rs[4:0]
Rd = (uns)Rt >> sa
Rd = (uns)Rt >> Rs[4:0]
NOP
Rt = (int)Rs - (int)Rd
Rt = (uns)Rs - (uns)Rd
Mem[Rs+offset] = Rt
Mem[Rs+offset] = Rt
Mem[Rs+offset] = Rt
Orders the cached coherent and
uncached loads and stores for access to
the shared memory
SystemCallException
if Rs == Rt
TrapException
if Rs == (int)Immed
TrapException
DS61143H-page 144
© 2011 Microchip Technology Inc.