PIC32MX320F032H_11 Datasheet, PDF (207/214 Pages) Microchip Technology – High-Performance, General Purpose and USB, 32-bit Flash Microcontrollers

PIC32MX3XX/4XX
Revision H (May 2011)
The revision includes the following global update:
• All references to VDDCORE/VCAP have been
changed to: VCORE/VCAP
• Added references to the new V-Temp temperature
range: -40ºC to +105ºC
This revision also includes minor typographical and
formatting changes throughout the data sheet text.
Major updates are referenced by their respective
section in the following table.
TABLE A-3: MAJOR SECTION UPDATES
Section Name
Update Description
Section 1.0 “Device Overview”
Section 4.0 “Memory Organization”
Updated the VBUS description in Table 1-1: “Pinout I/O Descriptions”.
Added Note 2 and changed the RIPL<2:0> bits to SRIPL<2:0> in the
Interrupt Register Map tables (see Table 4-2 through Table 4-6.
Added Note 2 to the Timer1-5 Register Map (see Table 4-7).
Updated the All Resets value for I2C1CON<15:0> and I2C2CON<15:0>
in the I2C1 and I2C2 Register Map (see Table 4-10).
Updated the All Resets value for SPI1STAT<15:0> and SPI2STAT<15:0>
in the SPI1 and SPI2 Register Map (see Table 4-12).
Updated the All Resets value for CM1CON<15:0> and CM2CON<15:0>
in the Comparator Register Map (see Table 4-17).
Renamed the RCDIV<2:0> bits to FRCDIV<2:0> and the LOCK bit to
SLOCK in the OSCCON register, and added Note 3 and the
SYSKEYregister to the System Control Registers Map (see Table 4-20).
Updated the All Resets value for the PMSTAT register in the Parallel
Master Port Register Map (see Table 4-37).
Updated the All Resets value for CHECON<15:0> and CHETAG<15:0>
in the Prefetch Register Map (see Table 4-39).
Renamed FUPLLEN, FUPLLIDIV, and FPLLMULT in the DEVCFG2
register to: UPLLEN, UPLLIDIV, and FPLLMUL, respectively in the
Device Configuration Word Summary (see Table 4-41).
Section 5.0 “Flash Program Memory”
Section 8.0 “Oscillator Configuration”
Section 11.0 “USB On-The-Go (OTG)”
Section 16.0 “Output Compare”
Section 22.0 “10-bit Analog-to-Digital
Converter (ADC)”
Section 26.0 “Special Features”
Added Notes 1 through 4 to the USB Register Map (see Table 4-43).
Added a note on Flash LVD Delay and Example 5-1.
Updated the PIC32MX3XX/4XX Family Clock Diagram (see Figure 8-1).
Updated the PIC32MX3XX/4XX Family USB Interface Diagram (see
Figure 11-1).
Updated the Output Compare Module Block Diagram (see Figure 16-1).
Updated the ADC Conversion Clock Period Block Diagram (see
Figure 22-2).
Renamed FUPLLEN, FUPLLIDIV, and FPLLMULT in the DEVCFG2
register to: UPLLEN, UPLLIDIV, and FPLLMUL, respectively (see
Register 26-3).
© 2011 Microchip Technology Inc.
DS61143H-page 207