PIC32MX320F032H_11 Datasheet, PDF (37/214 Pages) Microchip Technology – High-Performance, General Purpose and USB, 32-bit Flash Microcontrollers

PIC32MX3XX/4XX
3.0 CPU
Note 1: This data sheet summarizes the features
of the PIC32MX3XX/4XX family of
devices. It is not intended to be a compre-
hensive reference source. To comple-
ment the information in this data sheet,
refer to Section 2. “CPU” (DS61113) of
the “PIC32 Family Reference Manual”,
which is available from the Microchip web
site
(www.microchip.com/PIC32).
Resources for the MIPS32^® M4K^®
Processor Core are available at:
www.mips.com/products/cores/
32-64-bit-cores/mips32-m4k/.
2: Some registers and associated bits
described in this section may not be avail-
able on all devices. Refer to Section 4.0
“Memory Organization” in this data
sheet for device-specific register and bit
information.
The MIPS32^® M4K^® Processor Core is the heart of the
PIC32MX3XX/4XX family processor. The CPU fetches
instructions, decodes each instruction, fetches source
operands, executes each instruction and writes the
results of instruction execution to the proper destina-
tions.
3.1 Features
• 5-stage pipeline
• 32-bit Address and Data Paths
• MIPS32 Enhanced Architecture (Release 2)
- Multiply-Accumulate and Multiply-Subtract
Instructions
- Targeted Multiply Instruction
- Zero/One Detect Instructions
- WAIT Instruction
- Conditional Move Instructions (MOVN, MOVZ)
- Vectored interrupts
- Programmable exception vector base
FIGURE 3-1:
MIPS^® M4K^® BLOCK DIAGRAM
- Atomic interrupt enable/disable
- GPR shadow registers to minimize latency
for interrupt handlers
- Bit field manipulation instructions
• MIPS16e^® Code Compression
- 16-bit encoding of 32-bit instructions to
improve code density
- Special PC-relative instructions for efficient
loading of addresses and constants
- SAVE & RESTORE macro instructions for
setting up and tearing down stack frames
within subroutines
- Improved support for handling 8 and 16-bit
data types
• Simple Fixed Mapping Translation (FMT)
mechanism
• Simple Dual Bus Interface
- Independent 32-bit address and data busses
- Transactions can be aborted to improve
interrupt latency
• Autonomous Multiply/Divide Unit
- Maximum issue rate of one 32x16 multiply
per clock
- Maximum issue rate of one 32x32 multiply
every other clock
- Early-in iterative divide. Minimum 11 and
maximum 34 clock latency (dividend (rs) sign
extension-dependent)
• Power Control
- Minimum frequency: 0 MHz
- Low-Power mode (triggered by WAIT
instruction)
- Extensive use of local gated clocks
• EJTAG Debug and Instruction Trace
- Support for single stepping
- Virtual instruction and data address/value
- breakpoints
- PC tracing with trace compression
CPU
MDU
Execution
Core
(RF/ALU/Shift)
FMT
EJTAG
Trace
TAP
Trace I/F
Off-Chip
Debug I/F
Bus Interface
Dual Bus I/F
System
Coprocessor
Power
Mgmt.
© 2011 Microchip Technology Inc.
DS61143H-page 37