PIC32MX320F032H_11 Datasheet, PDF (39/214 Pages) Microchip Technology – High-Performance, General Purpose and USB, 32-bit Flash Microcontrollers

PIC32MX3XX/4XX
TABLE 3-1:
MIPS^® M4K^® PROCESSOR CORE HIGH-PERFORMANCE INTEGER
MULTIPLY/DIVIDE UNIT LATENCIES AND REPEAT RATES
Opcode
Operand Size (mul rt) (div rs)
Latency
Repeat Rate
MULT/MULTU, MADD/MADDU,
MSUB/MSUBU
16 bits
32 bits
1
1
2
2
MUL
16 bits
2
1
32 bits
3
2
DIV/DIVU
8 bits
12
11
16 bits
19
18
24 bits
26
25
32 bits
33
32
The MIPS architecture defines that the result of a mul-
tiply or divide operation be placed in the HI and LO reg-
isters. Using the Move-From-HI (MFHI) and Move-
From-LO (MFLO) instructions, these values can be
transferred to the general purpose register file.
the product to the current contents of the HI and LO
registers. Similarly, the MSUB instruction multiplies two
operands and then subtracts the product from the HI
and LO registers. The MADD and MSUB operations
are commonly used in DSP algorithms.
In addition to the HI/LO targeted operations, the
MIPS32 architecture also defines a multiply instruction,
MUL, which places the least significant results in the
primary register file instead of the HI/LO register pair.
By avoiding the explicit MFLO instruction, required
when using the LO register, and by supporting multiple
destination registers, the throughput of
multiply-intensive operations is increased.
Two other instructions, multiply-add (MADD) and multi-
ply-subtract (MSUB), are used to perform the multiply-
accumulate and multiply-subtract operations. The
MADD instruction multiplies two numbers and then adds
3.2.3
SYSTEM CONTROL
COPROCESSOR (CP0)
In the MIPS architecture, CP0 is responsible for the vir-
tual-to-physical address translation, the exception con-
trol system, the processor’s diagnostics capability, the
operating modes (kernel, user and debug), and
whether interrupts are enabled or disabled. Configura-
tion information, such as presence of options like
MIPS16e, is also available by accessing the CP0
registers, listed in Table 3-2.
TABLE 3-2: COPROCESSOR 0 REGISTERS
Register Register
Number Name
Function
0-6 Reserved
Reserved
7 HWREna
8
BadVAddr⁽¹⁾
9
Count⁽¹⁾
Enables access via the RDHWR instruction to selected hardware registers
Reports the address for the most recent address-related exception
Processor cycle count
10 Reserved
11 Compare⁽¹⁾
12 Status⁽¹⁾
12 IntCtl⁽¹⁾
12 SRSCtl⁽¹⁾
12 SRSMap⁽¹⁾
13 Cause⁽¹⁾
14
EPC⁽¹⁾
Reserved
Timer interrupt control
Processor status and control
Interrupt system status and control
Shadow register set status and control
Provides mapping from vectored interrupt to a shadow set
Cause of last general exception
Program counter at last exception
15 PRId
Processor identification and revision
15 EBASE
Exception vector base register
16 Config
Configuration register
16 Config1
Configuration register 1
16 Config2
Configuration register 2
16 Config3
Configuration register 3
© 2011 Microchip Technology Inc.
DS61143H-page 39