PIC32MX320F032H_11 Datasheet, PDF (103/214 Pages) Microchip Technology – High-Performance, General Purpose and USB, 32-bit Flash Microcontrollers

PIC32MX3XX/4XX
13.0 TIMER1
Note 1: This data sheet summarizes the features
of the PIC32MX3XX/4XX family of
devices. It is not intended to be a compre-
hensive reference source. To comple-
ment the information in this data sheet,
refer to Section 14. “Timers” (DS61105)
of the “PIC32 Family Reference Manual”,
which is available from the Microchip web
site (www.microchip.com/PIC32).
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
FIGURE 13-1:
TIMER1 BLOCK DIAGRAM⁽¹⁾
This family of PIC32MX devices features one
synchronous/asynchronous 16-bit timer that can oper-
ate as a free-running interval timer for various timing
applications and counting external events. This timer
can also be used with the Secondary Oscillator (SOSC)
for real-time clock applications. The following modes
are supported:
• Synchronous Internal Timer
• Synchronous Internal Gated Timer
• Synchronous External Timer
• Asynchronous External Timer
13.1 Additional Supported Features
• Selectable clock prescaler
• Timer operation during CPU Idle and Sleep mode
• Fast bit manipulation using CLR, SET and INV
registers
• Asynchronous mode can be used with the SOSC
to function as a Real-Time Clock (RTC)
PR1
Equal
16-bit Comparator
Reset
TMR1
0
T1IF
Event Flag
1
TGATE (T1CON<7>)
QD
Q
TSYNC (T1CON<2>)
1
Sync
0
TGATE (T1CON<7>)
TCS (T1CON<1>)
ON (T1CON<15>)
SOSCO/T1CK
SOSCI
x1
SOSCEN
Gate
Sync
10
PBCLK
00
Prescaler
1, 8, 64, 256
2
TCKPS<1:0>
(T1CON<5:4>)
Note 1: The default state of the SOSCEN (OSCCON<1>) during a device Reset is controlled by the FSOSCEN bit in
Configuration Word DEVCFG1.
© 2011 Microchip Technology Inc.
DS61143H-page 103