PIC32MX320F032H_11 Datasheet, PDF(69/214 Page) Microchip Technology – High-Performance, General Purpose and USB, 32-bit Flash Microcontrollers

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PIC32MX320F032H_11 Datasheet, PDF (69/214 Pages) Microchip Technology – High-Performance, General Purpose and USB, 32-bit Flash Microcontrollers

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TABLE 4-19: FLASH CONTROLLER REGISTERS MAP

Bits

31/15

30/14

29/13 28/12

27/11 26/10

25/9

24/8

23/7

22/6

21/5

20/4

19/3

18/2

17/1

16/0

F400 NVMCON(1) 31:16

15:0 WR

WREN WRERR LVDERR LVDSTAT

NVMOP<3:0>

31:16

F410 NVMKEY

15:0

NVMKEY<31:0>

F420 NVMADDR(1) 31:16

15:0

NVMADDR<31:0>

31:16

F430 NVMDATA

15:0

NVMDATA<31:0>

F440

NVMSRC

ADDR

31:16

15:0

NVMSRCADDR<31:0>

Legend:

x = unknown value on Reset, â = unimplemented, read as â0â. Reset values are shown in hexadecimal.

Note 1: This register has corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 âCLR, SET and INV Registersâ for more information.

0000

TABLE 4-20: SYSTEM CONTROL REGISTERS MAP(1,2)

Bits

31/15

30/14

29/13

28/12

27/11

26/10

25/9

24/8

23/7

22/6

21/5

20/4

19/3

18/2

17/1

16/0

31:16 â

F000 OSCCON

15:0

PLLODIV<2:0>

COSC<2:0>

FRCDIV<2:0>

NOSC<2:0>

â SOSCRDY â

CLKLOCK ULOCK SLOCK

PBDIV<1:0>

SLPEN

PLLMULT<2:0>

0000

UFRCEN SOSCEN OSWEN 0000

31:16 â

â 0000

F010 OSCTUN

15:0

TUN<5:0>

0000

31:16 â

â 0000

0000 WDTCON

15:0 ON

SWDTPS<4:0>

WDTCLR 0000

31:16 â

â 0000

F600 RCON

15:0

CMR VREGS EXTR

SWR

WDTO SLEEP

IDLE

BOR

POR 0000

31:16 â

â 0000

F610 RSWRST

15:0

SWRST 0000

F230 SYSKEY(3) 31:16

15:0

SYSKEY<31:0>

0000

Legend:

x = unknown value on Reset, â = unimplemented, read as â0â. Reset values are shown in hexadecimal.

Note 1:

Except where noted, all registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 âCLR, SET and INV

Registersâ for more information.

2: Reset values are dependent on the DEVCFGx Configuration bits and the type of reset.

3: This register does not have associated CLR, SET, and INV registers.

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