PIC18F2525_08 Datasheet, PDF (67/412 Pages) Microchip Technology – 28/40/44-Pin Enhanced Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology

PIC18F2525/2620/4525/4620
TABLE 5-2: REGISTER FILE SUMMARY (PIC18F2525/2620/4525/4620) (CONTINUED)
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on Details on
POR, BOR page:
SPBRGH EUSART Baud Rate Generator Register High Byte
0000 0000 51, 206
SPBRG EUSART Baud Rate Generator Register Low Byte
0000 0000 51, 206
RCREG EUSART Receive Register
0000 0000 51, 213
TXREG
EUSART Transmit Register
0000 0000 51, 211
TXSTA
CSRC
TX9
TXEN
SYNC
SENDB
BRGH
TRMT
TX9D 0000 0010 51, 202
RCSTA
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D 0000 000x 51, 203
EEADRH
—
—
—
—
—
—
EEPROM Addr Register High ---- --00 51, 73
EEADR
EEPROM Address Register
0000 0000 51, 80, 73
EEDATA EEPROM Data Register
0000 0000 51, 80, 73
EECON2 EEPROM Control Register 2 (not a physical register)
0000 0000 51, 80, 73
EECON1
EEPGD
CFGS
—
FREE
WRERR
WREN
WR
RD
xx-0 x000 51, 81, 74
IPR2
OSCFIP
CMIP
—
EEIP
BCLIP
HLVDIP
TMR3IP
CCP2IP 11-1 1111 52, 119
PIR2
OSCFIF
CMIF
—
EEIF
BCLIF
HLVDIF
TMR3IF
CCP2IF 00-0 0000 52, 115
PIE2
IPR1
PIR1
PIE1
OSCTUNE
TRISE⁽²⁾
TRISD⁽²⁾
OSCFIE
PSPIP⁽²⁾
PSPIF⁽²⁾
PSPIE⁽²⁾
INTSRC
CMIE
ADIP
ADIF
ADIE
PLLEN⁽³⁾
—
RCIP
RCIF
RCIE
—
IBF
OBF
IBOV
PORTD Data Direction Control Register
EEIE
TXIP
TXIF
TXIE
TUN4
PSPMODE
BCLIE
SSPIP
SSPIF
SSPIE
TUN3
—
HLVDIE
CCP1IP
CCP1IF
CCP1IE
TUN2
TRISE2
TMR3IE
TMR2IP
TMR2IF
TMR2IE
TUN1
TRISE1
CCP2IE
TMR1IP
TMR1IF
TMR1IE
TUN0
TRISE0
00-0 0000
1111 1111
0000 0000
0000 0000
00-0 0000
0000 -111
1111 1111
52, 117
52, 118
52, 114
52, 116
27, 52
52, 104
52, 100
TRISC
PORTC Data Direction Control Register
1111 1111 52, 97
TRISB
TRISA
LATE⁽²⁾
LATD⁽²⁾
PORTB Data Direction Control Register
TRISA7⁽⁵⁾ TRISA6⁽⁵⁾ Data Direction Control Register for PORTA
—
—
—
—
—
PORTE Data Latch Register
(Read and Write to Data Latch)
PORTD Data Latch Register (Read and Write to Data Latch)
1111 1111
1111 1111
---- -xxx
52, 94
52, 91
52, 103
xxxx xxxx 52, 100
LATC
PORTC Data Latch Register (Read and Write to Data Latch)
xxxx xxxx 52, 97
LATB
LATA
PORTE
PORTD⁽²⁾
PORTB Data Latch Register (Read and Write to Data Latch)
LATA7⁽⁵⁾ LATA6⁽⁵⁾ PORTA Data Latch Register (Read and Write to Data Latch)
—
—
—
—
RE3⁽⁴⁾
RE2⁽²⁾
RE1⁽²⁾
RD7
RD6
RD5
RD4
RD3
RD2
RD1
RE0⁽²⁾
RD0
xxxx xxxx
xxxx xxxx
---- xxxx
xxxx xxxx
52, 94
52, 91
52, 103
52, 100
PORTC
RC7
RC6
RC5
RC4
RC3
RC2
RC1
RC0 xxxx xxxx 52, 97
PORTB
PORTA
RB7
RA7⁽⁵⁾
RB6
RA6⁽⁵⁾
RB5
RA5
RB4
RA4
RB3
RA3
RB2
RA2
RB1
RA1
RB0 xxxx xxxx 52, 94
RA0 xx0x 0000 52, 91
Legend:
Note 1:
2:
3:
4:
5:
6:
x = unknown, u = unchanged, — = unimplemented, q = value depends on condition
The SBOREN bit is only available when the BOREN1:BOREN0 Configuration bits = 01; otherwise, it is disabled and reads as ‘0’. See
Section 4.4 “Brown-out Reset (BOR)”.
These registers and/or bits are not implemented on 28-pin devices and are read as ‘0’. Reset values are shown for 40/44-pin devices;
individual unimplemented bits should be interpreted as ‘-’.
The PLLEN bit is only available in specific oscillator configurations; otherwise, it is disabled and reads as ‘0’. See Section 2.6.4 “PLL in
INTOSC Modes”.
The RE3 bit is only available when Master Clear Reset is disabled (MCLRE Configuration bit = 0); otherwise, RE3 reads as ‘0’. This bit is
read-only.
RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary oscillator modes.
When disabled, these bits read as ‘0’.
Bit 7 and bit 6 are cleared by user software or by a POR.
© 2008 Microchip Technology Inc.
DS39626E-page 65