PIC18F2525_08 Datasheet, PDF (107/412 Pages) Microchip Technology – 28/40/44-Pin Enhanced Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology

PIC18F2525/2620/4525/4620
TABLE 9-9: PORTE I/O SUMMARY
Pin
Function
TRIS
Setting
I/O
I/O
Type
Description
RE0/RD/AN5
RE0
0
O
DIG LATE<0> data output; not affected by analog input.
1
I
ST PORTE<0> data input; disabled when analog input enabled.
RD
1
I
TTL PSP read enable input (PSP enabled).
AN5
1
I
ANA A/D input channel 5; default input configuration on POR.
RE1/WR/AN6
RE1
0
O
DIG LATE<1> data output; not affected by analog input.
1
I
ST PORTE<1> data input; disabled when analog input enabled.
WR
1
I
TTL PSP write enable input (PSP enabled).
AN6
1
I
ANA A/D input channel 6; default input configuration on POR.
RE2/CS/AN7
RE2
0
O
DIG LATE<2> data output; not affected by analog input.
1
I
ST PORTE<2> data input; disabled when analog input enabled.
CS
1
I
TTL PSP write enable input (PSP enabled).
AN7
1
I
ANA A/D input channel 7; default input configuration on POR.
MCLR/VPP/RE3⁽¹⁾ MCLR
—
I
ST External Master Clear input; enabled when MCLRE Configuration bit
is set.
VPP
—
I
ANA High-voltage detection; used for ICSP™ mode entry detection. Always
available, regardless of pin mode.
RE3
—⁽²⁾
I
ST PORTE<3> data input; enabled when MCLRE Configuration bit is
clear.
Legend:
Note 1:
2:
DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; ANA = Analog level input/output;
x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
RE3 is available on both 28-pin and 40/44-pin devices. All other PORTE pins are only implemented on 40/44-pin devices.
RE3 does not have a corresponding TRIS bit to control data direction.
TABLE 9-10: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values
on page
PORTE
—
—
—
LATE⁽²⁾
—
—
—
—
RE3^(1,2)
RE2
RE1
RE0
52
—
— PORTE Data Latch Register
52
TRISE
IBF
OBF
IBOV PSPMODE —
TRISE2 TRISE1 TRISE0
52
ADCON1
—
—
VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0
51
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTE.
Note 1: Implemented only when Master Clear functionality is disabled (MCLRE Configuration bit = 0).
2: RE3 is the only PORTE bit implemented on both 28-pin and 40/44-pin devices. All other bits are
implemented only when PORTE is implemented (i.e., 40/44-pin devices).
© 2008 Microchip Technology Inc.
DS39626E-page 105