PIC18F2525_08 Datasheet, PDF (234/412 Pages) Microchip Technology – 28/40/44-Pin Enhanced Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology

PIC18F2525/2620/4525/4620
19.8 Use of the CCP2 Trigger
An A/D conversion can be started by the Special Event
Trigger of the CCP2 module. This requires that the
CCP2M3:CCP2M0 bits (CCP2CON<3:0>) be
programmed as ‘1011’ and that the A/D module is
enabled (ADON bit is set). When the trigger occurs, the
GO/DONE bit will be set, starting the A/D acquisition
and conversion and the Timer1 (or Timer3) counter will
be reset to zero. Timer1 (or Timer3) is reset to automat-
ically repeat the A/D acquisition period with minimal
software overhead (moving ADRESH:ADRESL to the
desired location). The appropriate analog input
channel must be selected and the minimum acquisition
period is either timed by the user, or an appropriate
TACQ time selected before the Special Event Trigger
sets the GO/DONE bit (starts a conversion).
If the A/D module is not enabled (ADON is cleared), the
Special Event Trigger will be ignored by the A/D module
but will still reset the Timer1 (or Timer3) counter.
TABLE 19-2: REGISTERS ASSOCIATED WITH A/D OPERATION
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values
on page
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE
RBIE TMR0IF INT0IF
RBIF
49
PIR1
PSPIF⁽¹⁾
ADIF
RCIF
TXIF
SSPIF CCP1IF TMR2IF TMR1IF
52
PIE1
PSPIE⁽¹⁾ ADIE
RCIE
TXIE
SSPIE CCP1IE TMR2IE TMR1IE 52
IPR1
PSPIP⁽¹⁾ ADIP
RCIP
TXIP
SSPIP CCP1IP TMR2IP TMR1IP 52
PIR2
OSCFIF CMIF
—
EEIF
BCLIF HLVDIF TMR3IF CCP2IF
52
PIE2
OSCFIE CMIE
—
EEIE
BCLIE HLVDIE TMR3IE CCP2IE
52
IPR2
OSCFIP CMIP
—
EEIP
BCLIP HLVDIP TMR3IP CCP2IP
52
ADRESH A/D Result Register High Byte
51
ADRESL A/D Result Register Low Byte
51
ADCON0
—
—
CHS3
CHS2
CHS1 CHS0 GO/DONE ADON
51
ADCON1
—
—
VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0
51
ADCON2 ADFM
—
ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0
51
PORTA
RA7⁽¹⁾
RA6⁽¹⁾
RA5
RA4
RA3
RA2
RA1
RA0
52
TRISA
TRISA7⁽²⁾ TRISA6⁽²⁾ PORTA Data Direction Control Register
52
PORTB
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0
52
TRISB PORTB Data Direction Control Register
52
LATB
PORTB Data Latch Register (Read and Write to Data Latch)
52
PORTE⁽⁴⁾
—
—
—
—
RE3⁽³⁾
RE2
RE1
RE0
52
TRISE⁽⁴⁾
IBF
OBF
IBOV PSPMODE —
TRISE2 TRISE1 TRISE0
52
LATE⁽⁴⁾
—
—
—
—
— PORTE Data Latch Register
52
Legend:
Note 1:
2:
3:
4:
— = unimplemented, read as ‘0’. Shaded cells are not used for A/D conversion.
These bits are unimplemented on 28-pin devices; always maintain these bits clear.
PORTA<7:6> and their direction bits are individually configured as port pins based on various primary
oscillator modes. When disabled, these bits read as ‘0’.
RE3 port bit is available only as an input pin when the MCLRE Configuration bit is ‘0’.
These registers are not implemented on 28-pin devices.
DS39626E-page 232
© 2008 Microchip Technology Inc.