PIC18F2525_08 Datasheet, PDF (265/412 Pages) Microchip Technology – 28/40/44-Pin Enhanced Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology

PIC18F2525/2620/4525/4620
23.5 Program Verification and
Code Protection
The overall structure of the code protection on the
PIC18 Flash devices differs significantly from other
PIC^® devices.
The user program memory is divided into five blocks.
One of these is a boot block of 2 Kbytes. The remainder
of the memory is divided into four blocks on binary
boundaries.
Each of the five blocks has three code protection bits
associated with them. They are:
• Code-Protect bit (CPn)
• Write-Protect bit (WRTn)
• External Block Table Read bit (EBTRn)
Figure 23-5 shows the program memory organization
for 48 and 64-Kbyte devices and the specific code
protection bit associated with each block. The actual
locations of the bits are summarized in Table 23-3.
FIGURE 23-5:
CODE-PROTECTED PROGRAM MEMORY FOR PIC18F2525/2620/4525/4620
MEMORY SIZE/DEVICE
48 Kbytes
(PIC18F2525/4525)
64 Kbytes
Address
(PIC18F2620/4620) Range
Block Code Protection
Controlled By:
Boot Block
Block 0
Block 1
Block 2
Unimplemented
Read ‘0’s
Boot Block
Block 0
Block 1
Block 2
Block 3
000000h
0007FFh
000800h
003FFFh
004000h
007FFFh
008000h
00B7FFh
00C000h
00FFFFh
010000h
CPB, WRTB, EBTRB
CP0, WRT0, EBTR0
CP1, WRT1, EBTR1
CP2, WRT2, EBTR2
CP3, WRT3, EBTR3
Unimplemented
Read ‘0’s
Unimplemented
Read ‘0’s
(Unimplemented Memory Space)
1FFFFFh
TABLE 23-3: SUMMARY OF CODE PROTECTION REGISTERS
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
300008h CONFIG5L —
—
—
—
CP3⁽¹⁾
CP2
300009h CONFIG5H CPD
CPB
—
30000Ah CONFIG6L —
—
—
—
—
—
—
WRT3⁽¹⁾ WRT2
30000Bh CONFIG6H WRTD
30000Ch CONFIG7L —
WRTB
—
WRTC
—
—
—
—
—
EBTR3⁽¹⁾ EBTR2
30000Dh CONFIG7H —
EBTRB
—
—
—
—
Legend: Shaded cells are unimplemented.
Note 1: These bits are unimplemented in PIC18FX525 devices; maintain this bit set.
Bit 1
CP1
—
WRT1
—
EBTR1
—
Bit 0
CP0
—
WRT0
—
EBTR0
—
© 2008 Microchip Technology Inc.
DS39626E-page 263