PIC18F2525_08 Datasheet, PDF (187/412 Pages) Microchip Technology – 28/40/44-Pin Enhanced Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology

PIC18F2525/2620/4525/4620
17.4.6 MASTER MODE
Master mode is enabled by setting and clearing the
appropriate SSPM bits in SSPCON1 and by setting the
SSPEN bit. In Master mode, the SCL and SDA lines
are manipulated by the MSSP hardware.
Master mode of operation is supported by interrupt
generation on the detection of the Start and Stop
conditions. The Stop (P) and Start (S) bits are cleared
from a Reset or when the MSSP module is disabled.
Control of the I²C bus may be taken when the P bit is
set, or the bus is Idle, with both the S and P bits clear.
In Firmware Controlled Master mode, user code
conducts all I²C bus operations based on Start and
Stop bit conditions.
Once Master mode is enabled, the user has six
options.
1. Assert a Start condition on SDA and SCL.
2. Assert a Repeated Start condition on SDA and
SCL.
3. Write to the SSPBUF register initiating
transmission of data/address.
4. Configure the I²C port to receive data.
5. Generate an Acknowledge condition at the end
of a received byte of data.
6. Generate a Stop condition on SDA and SCL.
Note:
The MSSP module, when configured in
I²C Master mode, does not allow queueing
of events. For instance, the user is not
allowed to initiate a Start condition and
immediately write the SSPBUF register to
initiate transmission before the Start
condition is complete. In this case, the
SSPBUF will not be written to and the
WCOL bit will be set, indicating that a write
to the SSPBUF did not occur.
The following events will cause the MSSP Interrupt
Flag bit, SSPIF, to be set (MSSP interrupt, if enabled):
• Start condition
• Stop condition
• Data transfer byte transmitted/received
• Acknowledge transmit
• Repeated Start
FIGURE 17-16: MSSP BLOCK DIAGRAM (I²C™ MASTER MODE)
SDA
SDA In
Read
Internal
Data Bus
Write
SSPBUF
SSPSR
MSb
Shift
Clock
LSb
SSPM3:SSPM0
SSPADD<6:0>
Baud
Rate
Generator
SCL
Start bit, Stop bit,
Acknowledge
Generate
SCL In
Bus Collision
Start bit Detect
Stop bit Detect
Write Collision Detect
Clock Arbitration
State Counter for
end of XMIT/RCV
Set/Reset, S, P, WCOL (SSPSTAT);
Set SSPIF, BCLIF;
Reset ACKSTAT, PEN (SSPCON2)
© 2008 Microchip Technology Inc.
DS39626E-page 185