PIC18F2525_08 Datasheet, PDF (64/412 Pages) Microchip Technology – 28/40/44-Pin Enhanced Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology

PIC18F2525/2620/4525/4620
5.3.4 SPECIAL FUNCTION REGISTERS
The Special Function Registers (SFRs) are registers
used by the CPU and peripheral modules for controlling
the desired operation of the device. These registers are
implemented as static RAM. SFRs start at the top of
data memory (FFFh) and extend downward to occupy
the top half of Bank 15 (F80h to FFFh). A list of these
registers is given in Table 5-1 and Table 5-2.
The SFRs can be classified into two sets: those associ-
ated with the “core” device functionality (ALU, Resets
and interrupts) and those related to the peripheral
functions. The reset and interrupt registers are
described in their respective chapters, while the ALU’s
STATUS register is described later in this section.
Registers related to the operation of a peripheral feature
are described in the chapter for that peripheral.
The SFRs are typically distributed among the
peripherals whose functions they control. Unused SFR
locations are unimplemented and read as ‘0’s.
TABLE 5-1: SPECIAL FUNCTION REGISTER MAP FOR PIC18F2525/2620/4525/4620 DEVICES
Address
Name
FFFh TOSU
FFEh TOSH
FFDh
TOSL
FFCh STKPTR
FFBh PCLATU
FFAh PCLATH
FF9h
PCL
FF8h TBLPTRU
FF7h TBLPTRH
FF6h TBLPTRL
FF5h TABLAT
FF4h PRODH
FF3h PRODL
FF2h INTCON
FF1h INTCON2
FF0h INTCON3
FEFh INDF0⁽¹⁾
FEEh POSTINC0⁽¹⁾
FEDh POSTDEC0⁽¹⁾
FECh PREINC0⁽¹⁾
FEBh PLUSW0⁽¹⁾
FEAh FSR0H
FE9h FSR0L
FE8h WREG
FE7h INDF1⁽¹⁾
FE6h POSTINC1⁽¹⁾
FE5h POSTDEC1⁽¹⁾
FE4h PREINC1⁽¹⁾
FE3h PLUSW1⁽¹⁾
FE2h FSR1H
FE1h FSR1L
FE0h
BSR
Address
Name
FDFh INDF2⁽¹⁾
FDEh POSTINC2⁽¹⁾
FDDh POSTDEC2⁽¹⁾
FDCh PREINC2⁽¹⁾
FDBh PLUSW2⁽¹⁾
FDAh FSR2H
FD9h FSR2L
FD8h STATUS
FD7h TMR0H
FD6h TMR0L
FD5h
FD4h
T0CON
—⁽²⁾
FD3h OSCCON
FD2h HLVDCON
FD1h WDTCON
FD0h RCON
FCFh TMR1H
FCEh TMR1L
FCDh T1CON
FCCh TMR2
FCBh
PR2
FCAh T2CON
FC9h SSPBUF
FC8h SSPADD
FC7h SSPSTAT
FC6h SSPCON1
FC5h SSPCON2
FC4h ADRESH
FC3h ADRESL
FC2h ADCON0
FC1h ADCON1
FC0h ADCON2
Address
Name
FBFh CCPR1H
FBEh CCPR1L
FBDh CCP1CON
FBCh CCPR2H
FBBh CCPR2L
FBAh CCP2CON
FB9h
—⁽²⁾
FB8h BAUDCON
FB7h PWM1CON⁽³⁾
FB6h ECCP1AS⁽³⁾
FB5h CVRCON
FB4h CMCON
FB3h TMR3H
FB2h TMR3L
FB1h T3CON
FB0h SPBRGH
FAFh SPBRG
FAEh RCREG
FADh TXREG
FACh TXSTA
FABh RCSTA
FAAh EEADRH
FA9h EEADR
FA8h EEDATA
FA7h EECON2⁽¹⁾
FA6h
FA5h
FA4h
FA3h
EECON1
—⁽²⁾
—⁽²⁾
—⁽²⁾
FA2h
IPR2
FA1h
PIR2
FA0h
PIE2
Address
F9Fh
F9Eh
F9Dh
F9Ch
F9Bh
F9Ah
F99h
F98h
F97h
F96h
F95h
F94h
F93h
F92h
F91h
F90h
F8Fh
F8Eh
F8Dh
F8Ch
F8Bh
F8Ah
F89h
F88h
F87h
F86h
F85h
F84h
F83h
F82h
F81h
F80h
Name
IPR1
PIR1
PIE1
—⁽²⁾
OSCTUNE
—⁽²⁾
—⁽²⁾
—⁽²⁾
—⁽²⁾
TRISE⁽³⁾
TRISD⁽³⁾
TRISC
TRISB
TRISA
—⁽²⁾
—⁽²⁾
—⁽²⁾
—⁽²⁾
LATE⁽³⁾
LATD⁽³⁾
LATC
LATB
LATA
—⁽²⁾
—⁽²⁾
—⁽²⁾
—⁽²⁾
PORTE⁽³⁾
PORTD⁽³⁾
PORTC
PORTB
PORTA
Note 1: This is not a physical register.
2: Unimplemented registers are read as ‘0’.
3: This register is not available on 28-pin devices.
DS39626E-page 62
© 2008 Microchip Technology Inc.