PIC24F16KL402 Datasheet, PDF (61/260 Pages) Microchip Technology – Low-Power, Low-Cost, General Purpose 16-Bit Flash Microcontrollers with nanoWatt XLP Technology

PIC24F16KL402 FAMILY
REGISTER 7-1: RCON: RESET CONTROL REGISTER⁽¹⁾ (CONTINUED)
bit 3
SLEEP: Wake-up from Sleep Flag bit
1 = Device has been in Sleep mode
0 = Device has not been in Sleep mode
bit 2
IDLE: Wake-up from Idle Flag bit
1 = Device has been in Idle mode
0 = Device has not been in Idle mode
bit 1
BOR: Brown-out Reset Flag bit
1 = A Brown-out Reset has occurred (the BOR is also set after a POR)
0 = A Brown-out Reset has not occurred
bit 0
POR: Power-on Reset Flag bit
1 = A Power-up Reset has occurred
0 = A Power-up Reset has not occurred
Note 1:
2:
3:
All of the Reset status bits may be set or cleared in software. Setting one of these bits in software does not
cause a device Reset.
If the FWDTEN Configuration bit is ‘1’ (unprogrammed), the WDT is always enabled, regardless of the
SWDTEN bit setting.
The SBOREN bit is forced to ‘0’ when disabled by the Configuration bits, BOREN<1:0> (FPOR<1:0>).
When the Configuration bits are set to enable SBOREN, the default Reset state will be ‘1’.
TABLE 7-1: RESET FLAG BIT OPERATION
Flag Bit
Setting Event
TRAPR (RCON<15>)
Trap Conflict Event
IOPUWR (RCON<14>)
Illegal Opcode or Uninitialized W Register Access
CM (RCON<9>)
Configuration Mismatch Reset
EXTR (RCON<7>)
MCLR Reset
SWR (RCON<6>)
WDTO (RCON<4>)
RESET Instruction
WDT Time-out
SLEEP (RCON<3>)
IDLE (RCON<2>)
BOR (RCON<1>)
PWRSAV #SLEEP Instruction
PWRSAV #IDLE Instruction
POR, BOR
POR (RCON<0>)
POR
Note: All Reset flag bits may be set or cleared by the user software.
Clearing Event
POR
POR
POR
POR
POR
PWRSAV Instruction, POR
POR
POR
—
—
7.1 Clock Source Selection at Reset
If clock switching is enabled, the system clock source at
device Reset is chosen, as shown in Table 7-2. If clock
switching is disabled, the system clock source is always
selected according to the oscillator Configuration bits.
For more information, see Section 9.0 “Oscillator
Configuration”.
TABLE 7-2:
Reset Type
POR
BOR
MCLR
WDTO
SWR
OSCILLATOR SELECTION vs.
TYPE OF RESET (CLOCK
SWITCHING ENABLED)
Clock Source Determinant
FNOSC Configuration bits
(FNOSC<10:8>)
COSC Control bits
(OSCCON<14:12>)
 2011 Microchip Technology Inc.
DS31037B-page 61