PIC24F16KL402 Datasheet, PDF (139/260 Pages) Microchip Technology – Low-Power, Low-Cost, General Purpose 16-Bit Flash Microcontrollers with nanoWatt XLP Technology

PIC24F16KL402 FAMILY
REGISTER 17-2: SSPxSTAT: MSSPx STATUS REGISTER (I²C™ MODE)
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
bit 15
U-0
—
bit 8
R/W-0
R/W-0
R-0
R-0
R-0
R-0
R-0
R-0
SMP
CKE
D/A
P⁽¹⁾
S⁽¹⁾
R/W
UA
BF
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-8
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
Unimplemented: Read as ‘0’
SMP: Slew Rate Control bit
In Master or Slave mode:
1 = Slew rate control is disabled for Standard Speed mode (100 kHz and 1 MHz)
0 = Slew rate control is enabled for High-Speed mode (400 kHz)
CKE: SMBus Select bit
In Master or Slave mode:
1 = Enable SMBus specific inputs
0 = Disable SMBus specific inputs
D/A: Data/Address bit
In Master mode:
Reserved.
In Slave mode:
1 = Indicates that the last byte received or transmitted was data
0 = Indicates that the last byte received or transmitted was address
P: Stop bit⁽¹⁾
1 = Indicates that a Stop bit has been detected last
0 = Stop bit was not detected last
S: Start bit⁽¹⁾
1 = Indicates that a Start bit has been detected last
0 = Start bit was not detected last
R/W: Read/Write Information bit
In Slave mode:⁽²⁾
1 = Read
0 = Write
In Master mode:⁽³⁾
1 = Transmit is in progress
0 = Transmit is not in progress
UA: Update Address bit (10-bit Slave mode only)
1 = Indicates that the user needs to update the address in the SSPxADD register
0 = Address does not need to be updated
Note 1:
2:
3:
This bit is cleared on RESET and when SSPEN is cleared.
This bit holds the R/W bit information following the last address match. This bit is only valid from the
address match to the next Start bit, Stop bit or not ACK bit.
ORing this bit with SEN, RSEN, PEN, RCEN or ACKEN will indicate if the MSSPx is in Active mode.
 2011 Microchip Technology Inc.
DS31037B-page 139