PIC24F16KL402 Datasheet, PDF (145/260 Pages) Microchip Technology – Low-Power, Low-Cost, General Purpose 16-Bit Flash Microcontrollers with nanoWatt XLP Technology

PIC24F16KL402 FAMILY
REGISTER 17-7: SSPxCON3: MSSPx CONTROL REGISTER 3 (I²C™ MODE)
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
bit 15
U-0
—
bit 8
R-0
ACKTIM⁽¹⁾
bit 7
R/W-0
PCIE
R/W-0
SCIE
R/W-0
BOEN
R/W-0
SDAHT
R/W-0
SBCDE
R/W-0
AHEN
R/W-0
DHEN
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-8
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Unimplemented: Read as ‘0’
ACKTIM: Acknowledge Time Status bit⁽¹⁾
1 = Indicates the I²C bus is in an Acknowledge sequence, set on the 8^th falling edge of the SCLx clock
0 = Not an Acknowledge sequence, cleared on 9^th rising edge of SCLx clock
PCIE: Stop Condition Interrupt Enable bit
1 = Enable interrupt on detection of Stop condition
0 = Stop detection interrupts are disabled⁽²⁾
SCIE: Start Condition Interrupt Enable bit
1 = Enable interrupt on detection of Start or Restart conditions
0 = Start detection interrupts are disabled⁽²⁾
BOEN: Buffer Overwrite Enable bit
I.²C Master mode:
This bit is ignored.
I²C Slave mode:
1 = SSPxBUF is updated and an ACK is generated for a received address/data byte, ignoring the state
of the SSPxOV bit only if the BF bit = 0
0 = SSPxBUF is only updated when SSPxOV is clear
SDAHT: SDAx Hold Time Selection bit
1 = Minimum of 300 ns hold time on SDAx after the falling edge of SCLx
0 = Minimum of 100 ns hold time on SDAx after the falling edge of SCLx
SBCDE: Slave Mode Bus Collision Detect Enable bit (Slave mode only)
1 = Enables slave bus collision interrupts
0 = Slave bus collision interrupts are disabled
AHEN: Address Hold Enable bit (Slave mode only)
1 = Following the 8th falling edge of SCLx for a matching received address byte; CKP bit of the
SSPxCON1 register will be cleared and the SCLx will be held low.
0 = Address holding is disabled
DHEN: Data Hold Enable bit (Slave mode only)
1 = Following the 8th falling edge of SCLx for a received data byte; slave hardware clears the CKP bit
of the SSPxCON1 register and SCLx is held low.
0 = Data holding is disabled
Note 1: This bit has no effect in Slave modes for which Start and Stop condition detection is explicitly listed as
enabled.
2: The ACKTIM status bit is active only when the AHEN bit or DHEN bit is set.
 2011 Microchip Technology Inc.
DS31037B-page 145