PIC24F16KL402 Datasheet, PDF (60/260 Pages) Microchip Technology – Low-Power, Low-Cost, General Purpose 16-Bit Flash Microcontrollers with nanoWatt XLP Technology

PIC24F16KL402 FAMILY
REGISTER 7-1: RCON: RESET CONTROL REGISTER⁽¹⁾
R/W-0
R/W-0
R/W-0⁽³⁾
U-0
U-0
U-0
R/W-0
R/W-0
TRAPR
IOPUWR SBOREN
—
—
—
CM
PMSLP
bit 15
bit 8
R/W-0
EXTR
bit 7
R/W-0
SWR
R/W-0
SWDTEN⁽²⁾
R/W-0
WDTO
R/W-0
SLEEP
R/W-0
IDLE
R/W-1
BOR
R/W-1
POR
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
bit 14
bit 13
bit 12-10
bit 9
bit 8
bit 7
bit 6
bit 5
bit 4
TRAPR: Trap Reset Flag bit
1 = A Trap Conflict Reset has occurred
0 = A Trap Conflict Reset has not occurred
IOPUWR: Illegal Opcode or Uninitialized W Access Reset Flag bit
1 = An illegal opcode detection, an illegal address mode or an uninitialized W register is used as an
Address Pointer and caused a Reset
0 = An illegal opcode or uninitialized W Reset has not occurred
SBOREN: Software Enable/Disable of BOR bit⁽³⁾
1 = BOR is turned on in software
0 = BOR is turned off in software
Unimplemented: Read as ‘0’
CM: Configuration Word Mismatch Reset Flag bit
1 = A Configuration Word Mismatch Reset has occurred
0 = A Configuration Word Mismatch Reset has not occurred
PMSLP: Program Memory Power During Sleep bit
1 = Program memory bias voltage remains powered during Sleep
0 = Program memory bias voltage is powered down during Sleep
EXTR: External Reset (MCLR) Pin bit
1 = A Master Clear (pin) Reset has occurred
0 = A Master Clear (pin) Reset has not occurred
SWR: Software Reset (Instruction) Flag bit
1 = A RESET instruction has been executed
0 = A RESET instruction has not been executed
SWDTEN: Software Enable/Disable of WDT bit⁽²⁾
1 = WDT is enabled
0 = WDT is disabled
WDTO: Watchdog Timer Time-out Flag bit
1 = WDT time-out has occurred
0 = WDT time-out has not occurred
Note 1:
2:
3:
All of the Reset status bits may be set or cleared in software. Setting one of these bits in software does not
cause a device Reset.
If the FWDTEN Configuration bit is ‘1’ (unprogrammed), the WDT is always enabled, regardless of the
SWDTEN bit setting.
The SBOREN bit is forced to ‘0’ when disabled by the Configuration bits, BOREN<1:0> (FPOR<1:0>).
When the Configuration bits are set to enable SBOREN, the default Reset state will be ‘1’.
DS31037B-page 60
 2011 Microchip Technology Inc.