PIC24F16KL402 Datasheet, PDF (144/260 Pages) Microchip Technology – Low-Power, Low-Cost, General Purpose 16-Bit Flash Microcontrollers with nanoWatt XLP Technology

PIC24F16KL402 FAMILY
REGISTER 17-6: SSPxCON3: MSSPx CONTROL REGISTER 3 (SPI MODE)
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
bit 15
U-0
—
bit 8
R-0
ACKTIM
bit 7
R/W-0
PCIE
R/W-0
SCIE
R/W-0
BOEN⁽¹⁾
R/W-0
SDAHT
R/W-0
SBCDE
R/W-0
AHEN
R/W-0
DHEN
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-8
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Unimplemented: Read as ‘0’
ACKTIM: Acknowledge Time Status bit (I²C™ mode only)
Unused in SPI mode.
PCIE: Stop Condition Interrupt Enable bit (I²C mode only)
Unused in SPI mode.
SCIE: Start Condition Interrupt Enable bit (I²C mode only)
Unused in SPI mode.
BOEN: Buffer Overwrite Enable bit⁽¹⁾
In SPI Slave mode:
1 = SSPxBUF updates every time that a new data byte is shifted in, ignoring the BF bit
0 = If a new byte is received with the BF bit of the SSPxSTAT register already set, the SSPxOV bit of
the SSPxCON1 register is set and the buffer is not updated
SDAHT: SDAx Hold Time Selection bit (I²C mode only)
Unused in SPI mode.
SBCDE: Slave Mode Bus Collision Detect Enable bit (I²C Slave mode only)
Unused in SPI mode.
AHEN: Address Hold Enable bit (I²C Slave mode only)
Unused in SPI mode.
DHEN: Data Hold Enable bit (Slave mode only)
Unused in SPI mode.
Note 1: For daisy-chained SPI operation: Allows the user to ignore all but the last received byte. SSPxOV is still
set when a new byte is received and BF = 1, but hardware continues to write the most recent byte to
SSPxBUF.
DS31037B-page 144
 2011 Microchip Technology Inc.