PIC24F16KL402 Datasheet, PDF (31/260 Pages) Microchip Technology – Low-Power, Low-Cost, General Purpose 16-Bit Flash Microcontrollers with nanoWatt XLP Technology

PIC24F16KL402 FAMILY
4.0 MEMORY ORGANIZATION
As Harvard architecture devices, the PIC24F
microcontrollers feature separate program and data
memory space and bussing. This architecture also
allows the direct access of program memory from the
data space during code execution.
4.1 Program Address Space
The program address memory space of the
PIC24F16KL402 family is 4M instructions. The space is
addressable by a 24-bit value derived from either the
23-bit Program Counter (PC) during program execution,
or from a table operation or data space remapping, as
described in Section 4.3 “Interfacing Program and
Data Memory Spaces”.
User access to the program memory space is restricted
to the lower half of the address range (000000h to
7FFFFFh). The exception is the use of TBLRD/TBLWT
operations, which use TBLPAG<7> to permit access to
the Configuration bits and Device ID sections of the
configuration memory space.
Memory maps for the PIC24F16KL402 family of
devices are shown in Figure 4-1.
FIGURE 4-1:
PROGRAM SPACE MEMORY MAP FOR PIC24F16KL402 FAMILY DEVICES
PIC24F04KLXXX
GOTO Instruction
Reset Address
Interrupt Vector Table
Reserved
Alternate Vector Table
Flash
Program Memory
(1408 instructions)
PIC24F08KL2XX
GOTO Instruction
Reset Address
Interrupt Vector Table
Reserved
Alternate Vector Table
Flash
Program Memory
(2816 instructions)
PIC24F08KL3XX
GOTO Instruction
Reset Address
Interrupt Vector Table
Reserved
Alternate Vector Table
Flash
Program Memory
(2816 instructions)
PIC24F08KL4XX
GOTO Instruction
Reset Address
Interrupt Vector Table
Reserved
Alternate Vector Table
Flash
Program Memory
(2816 instructions)
PIC24F16KLXXX
GOTO Instruction
Reset Address
Interrupt Vector Table
Reserved
Alternate Vector Table
000000h
000002h
000004h
0000FEh
000100h
000104h
0001FEh
000200h
Flash
Program Memory
(5632 instructions)
000AFEh
0015FEh
Unimplemented
Read ‘0’
Reserved
Unique ID
Reserved
Device Config Registers
Unimplemented
Read ‘0’
Reserved
Unique ID
Reserved
Device Config Registers
Unimplemented
Read ‘0’
Data EEPROM
(256 bytes)
Reserved
Unique ID
Reserved
Device Config Registers
Unimplemented
Read ‘0’
Data EEPROM
(512 bytes)
Reserved
Unique ID
Reserved
Device Config Registers
Unimplemented
Read ‘0’
Data EEPROM
(512 bytes)
Reserved
Unique ID
Reserved
Device Config Registers
002BFEh
7FFE00h
7FFF00h
7FFFFFh
800000h
800800h
800802h
800808h
80080Ah
F80000h
F8000Eh
F80010h
Reserved
Reserved
Reserved
Reserved
Reserved
DEVID (2)
DEVID (2)
DEVID (2)
DEVID (2)
DEVID (2)
FEFFFEh
FF0000h
FFFFFFh
Note: Memory areas are not displayed to scale.
DS31037B-page 31
 2011 Microchip Technology Inc.