PIC24FJ256GB110-I Datasheet, PDF (34/328 Pages) Microchip Technology – 64/80/100-Pin, 16-Bit Flash Microcontrollers with USB On-The-Go (OTG)

PIC24FJ256GB110 FAMILY
3.1.1
PROGRAM MEMORY
ORGANIZATION
The program memory space is organized in
word-addressable blocks. Although it is treated as
24 bits wide, it is more appropriate to think of each
address of the program memory as a lower and upper
word, with the upper byte of the upper word being
unimplemented. The lower word always has an even
address, while the upper word has an odd address
(Figure 3-2).
Program memory addresses are always word-aligned
on the lower word, and addresses are incremented or
decremented by two during code execution. This
arrangement also provides compatibility with data
memory space addressing and makes it possible to
access data in the program memory space.
3.1.2 HARD MEMORY VECTORS
All PIC24F devices reserve the addresses between
00000h and 000200h for hard coded program execu-
tion vectors. A hardware Reset vector is provided to
redirect code execution from the default value of the
PC on device Reset to the actual start of code. A GOTO
instruction is programmed by the user at 000000h with
the actual address for the start of code at 000002h.
PIC24F devices also have two interrupt vector tables,
located from 000004h to 0000FFh and 000100h to
0001FFh. These vector tables allow each of the many
device interrupt sources to be handled by separate
ISRs. A more detailed discussion of the interrupt vector
tables is provided in Section 6.1 “Interrupt Vector
Table”.
3.1.3 FLASH CONFIGURATION WORDS
In PIC24FJ256GB110 family devices, the top three
words of on-chip program memory are reserved for
configuration information. On device Reset, the config-
uration information is copied into the appropriate
Configuration registers. The addresses of the Flash
Configuration Word for devices in the
PIC24FJ256GB110 family are shown in Table 3-1.
Their location in the memory map is shown with the
other memory vectors in Figure 3-1.
The Configuration Words in program memory are a
compact format. The actual Configuration bits are
mapped in several different registers in the configuration
memory space. Their order in the Flash Configuration
Words do not reflect a corresponding arrangement in the
configuration space. Additional details on the device
Configuration Words are provided in Section 25.1
“Configuration Bits”.
TABLE 3-1:
FLASH CONFIGURATION
WORDS FOR
PIC24FJ256GB110 FAMILY
DEVICES
Device
Program
Memory
(Words)
Configuration
Word
Addresses
PIC24FJ64GB
PIC24FJ128GB
PIC24FJ192GB
PIC24FJ256GB
22,016
44,032
67,072
87,552
00ABFAh:
00ABFEh
0157FAh:
0157FEh
020BFAh:
020BFEh
02ABFAh:
02ABFEh
FIGURE 3-2:
MSW
Address
000001h
000003h
000005h
000007h
PROGRAM MEMORY ORGANIZATION
most significant word
least significant word
23
16
8
00000000
00000000
00000000
00000000
Program Memory
‘Phantom’ Byte
(read as ‘0’)
Instruction Width
PC Address
(LSW Address)
0
000000h
000002h
000004h
000006h
DS39897B-page 32
Preliminary
© 2008 Microchip Technology Inc.