PIC24FJ256GB110-I Datasheet, PDF (12/328 Pages) Microchip Technology – 64/80/100-Pin, 16-Bit Flash Microcontrollers with USB On-The-Go (OTG)

PIC24FJ256GB110 FAMILY
1.2 USB On-The-Go
With the PIC24FJ256GB110 family of devices,
Microchip introduces USB On-The-Go functionality on
a single chip to its product line. This new module
provides on-chip functionality as a target device com-
patible with the USB 2.0 standard, as well as limited
stand-alone functionality as a USB embedded host. By
implementing USB Host Negotiation Protocol (HNP),
the module can also dynamically switch between
device and host operation, allowing for a much wider
range of versatile USB-enabled applications on a
microcontroller platform.
In addition to USB host functionality, PIC24FJ256GB110
family devices provide a true single-chip USB solution,
including an on-chip transceiver and voltage regulator,
and a voltage boost generator for sourcing bus power
during host operations.
1.3 Other Special Features
• Peripheral Pin Select: The peripheral pin select
feature allows most digital peripherals to be
mapped over a fixed set of digital I/O pins. Users
may independently map the input and/or output of
any one of the many digital peripherals to any one
of the I/O pins.
• Communications: The PIC24FJ256GB110 family
incorporates a range of serial communication
peripherals to handle a range of application
requirements. There are three independent I²C
modules that support both Master and Slave
modes of operation. Devices also have, through
the peripheral pin select feature, four independent
UARTs with built-in IrDA encoder/decoders and
three SPI modules.
• Analog Features: All members of the
PIC24FJ256GB110 family include a 10-bit A/D
Converter module and a triple comparator
module. The A/D module incorporates program-
mable acquisition time, allowing for a channel to
be selected and a conversion to be initiated
without waiting for a sampling period, as well as
faster sampling speeds. The comparator module
includes three analog comparators that are
configurable for a wide range of operations.
• CTMU Interface: In addition to their other analog
features, members of the PIC24FJ256GB110
family include the brand new CTMU interface
module. This provides a convenient method for
precision time measurement and pulse genera-
tion, and can serve as an interface for capacitive
sensors.
• Parallel Master/Enhanced Parallel Slave Port:
One of the general purpose I/O ports can be
reconfigured for enhanced parallel data communi-
cations. In this mode, the port can be configured
for both master and slave operations, and
supports 8-bit and 16-bit data transfers with up to
16 external address lines in Master modes.
• Real-Time Clock/Calendar: This module
implements a full-featured clock and calendar with
alarm functions in hardware, freeing up timer
resources and program memory space for use of
the core application.
1.4 Details on Individual Family
Members
Devices in the PIC24FJ256GB110 family are available
in 64-pin, 80-pin and 100-pin packages. The general
block diagram for all devices is shown in Figure 1-1.
The devices are differentiated from each other in four
ways:
1. Flash program memory (64 Kbytes for
PIC24FJ64GB1 devices, 128 Kbytes for
PIC24FJ128GB1 devices, 192 Kbytes for
PIC24FJ192GB1 devices and 256 Kbytes for
PIC24FJ256GB1 devices).
2. Available I/O pins and ports (51 pins on 6 ports
for 64-pin devices, 65 pins on 7 ports for 80-pin
devices and 83 pins on 7 ports for 100-pin
devices).
3. Available Interrupt-on-Change Notification (ICN)
inputs (49 on 64-pin devices, 63 on 80-pin
devices, and 81 on 100-pin devices).
4. Available remappable pins (29 pins on 64-pin
devices, 40 pins on 80-pin devices and 44 pins
on 100-pin devices)
All other features for devices in this family are identical.
These are summarized in Table 1-1.
A list of the pin features available on the
PIC24FJ256GB110 family devices, sorted by function,
is shown in Table 1-4. Note that this table shows the pin
location of individual peripheral features and not how
they are multiplexed on the same pin. This information
is provided in the pinout diagrams in the beginning of
the data sheet. Multiplexed features are sorted by the
priority given to a feature, with the highest priority
peripheral being listed first.
DS39897B-page 10
Preliminary
© 2008 Microchip Technology Inc.