PIC24FJ256GB110-I Datasheet, PDF (261/328 Pages) Microchip Technology – 64/80/100-Pin, 16-Bit Flash Microcontrollers with USB On-The-Go (OTG)

PIC24FJ256GB110 FAMILY
22.0 TRIPLE COMPARATOR
MODULE
Note:
This data sheet summarizes the features
of this group of PIC24F devices. It is not
intended to be a comprehensive reference
source. For more information, refer to the
associated “PIC24F Family Reference
Manual” chapter.
The triple comparator module provides three dual input
comparators. The inputs to the comparator can be con-
figured to use any one of four external analog inputs as
well, as a voltage reference input from either the
internal band gap reference divided by two (VBG/2) or
the comparator voltage reference generator.
The comparator outputs may be directly connected to
the CxOUT pins. When the respective COE equals ‘1’,
the I/O pad logic makes the unsynchronized output of
the comparator available on the pin.
A simplified block diagram of the module in shown in
Figure 22-1. Diagrams of the possible individual
comparator configurations are shown in Figure 22-2.
Each comparator has its own control register,
CMxCON (Register 22-1), for enabling and configuring
its operation. The output and event status of all three
comparators is provided in the CMSTAT register
(Register 22-2).
FIGURE 22-1:
TRIPLE COMPARATOR MODULE BLOCK DIAGRAM
CCH1:CCH0
CREF
CXINB
CXINC
CXIND
VBG/2
Input
Select
Logic
VIN-
VIN+ ^C1
VIN-
VIN+ ^C2
EVPOL1:EVPOL0
CPOL
Trigger/Interrupt
Logic
CEVT
COE
C1OUT
COUT ^Pin
EVPOL1:EVPOL0
CPOL
Trigger/Interrupt
Logic
CEVT
COE
C2OUT
COUT ^Pin
CXINA
CVREF
VIN-
VIN+ ^C3
EVPOL1:EVPOL0
CPOL
Trigger/Interrupt
Logic
CEVT
COE
C3OUT
COUT ^Pin
© 2008 Microchip Technology Inc.
Preliminary
DS39897B-page 259