PIC24FJ256GB110-I Datasheet, PDF (192/328 Pages) Microchip Technology – 64/80/100-Pin, 16-Bit Flash Microcontrollers with USB On-The-Go (OTG)

PIC24FJ256GB110 FAMILY
REGISTER 16-1: UxMODE: UARTx MODE REGISTER
R/W-0
U-0
UARTEN⁽¹⁾
—
bit 15
R/W-0
R/W-0
R/W-0
U-0
USIDL
IREN⁽²⁾
RTSMD
—
R/W-0
UEN1
R/W-0
UEN0
bit 8
R/C-0, HC
WAKE
bit 7
R/W-0
LPBACK
R/W-0, HC
ABAUD
R/W-0
RXINV
R/W-0
BRGH
R/W-0
PDSEL1
R/W-0
PDSEL0
R/W-0
STSEL
bit 0
Legend:
R = Readable bit
-n = Value at POR
C = Clearable bit
W = Writable bit
‘1’ = Bit is set
HC = Hardware Clearable bit
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9-8
bit 7
bit 6
bit 5
UARTEN: UARTx Enable bit⁽¹⁾
1 = UARTx is enabled; all UARTx pins are controlled by UARTx as defined by UEN1:UEN0
0 = UARTx is disabled; all UARTx pins are controlled by PORT latches; UARTx power consumption
minimal
Unimplemented: Read as ‘0’
USIDL: Stop in Idle Mode bit
1 = Discontinue module operation when device enters Idle mode
0 = Continue module operation in Idle mode
IREN: IrDA^® Encoder and Decoder Enable bit⁽²⁾
1 = IrDA encoder and decoder enabled
0 = IrDA encoder and decoder disabled
RTSMD: Mode Selection for UxRTS Pin bit
1 = UxRTS pin in Simplex mode
0 = UxRTS pin in Flow Control mode
Unimplemented: Read as ‘0’
UEN1:UEN0: UARTx Enable bits
11 = UxTX, UxRX and BCLKx pins are enabled and used; UxCTS pin controlled by PORT latches
10 = UxTX, UxRX, UxCTS and UxRTS pins are enabled and used
01 = UxTX, UxRX and UxRTS pins are enabled and used; UxCTS pin controlled by PORT latches
00 = UxTX and UxRX pins are enabled and used; UxCTS and UxRTS/BCLKx pins controlled by PORT
latches
WAKE: Wake-up on Start Bit Detect During Sleep Mode Enable bit
1 = UARTx will continue to sample the UxRX pin; interrupt generated on falling edge, bit cleared in
hardware on following rising edge
0 = No wake-up enabled
LPBACK: UARTx Loopback Mode Select bit
1 = Enable Loopback mode
0 = Loopback mode is disabled
ABAUD: Auto-Baud Enable bit
1 = Enable baud rate measurement on the next character – requires reception of a Sync field (55h);
cleared in hardware upon completion
0 = Baud rate measurement disabled or completed
Note 1: If UARTEN = 1, the peripheral inputs and outputs must be configured to an available RPn pin.
See Section 9.4 “Peripheral Pin Select” for more information.
2: This feature is only available for the 16x BRG mode (BRGH = 0).
DS39897B-page 190
Preliminary
© 2008 Microchip Technology Inc.