PIC24FJ256GB110-I Datasheet, PDF (33/328 Pages) Microchip Technology – 64/80/100-Pin, 16-Bit Flash Microcontrollers with USB On-The-Go (OTG)

PIC24FJ256GB110 FAMILY
3.0 MEMORY ORGANIZATION
As Harvard architecture devices, PIC24F micro-
controllers feature separate program and data memory
spaces and busses. This architecture also allows the
direct access of program memory from the data space
during code execution.
3.1 Program Address Space
The program address memory space of the
PIC24FJ256GB110 family devices is 4M instructions.
The space is addressable by a 24-bit value derived
from either the 23-bit Program Counter (PC) during pro-
gram execution, or from table operation or data space
remapping, as described in Section 3.3 “Interfacing
Program and Data Memory Spaces”.
User access to the program memory space is restricted
to the lower half of the address range (000000h to
7FFFFFh). The exception is the use of TBLRD/TBLWT
operations which use TBLPAG<7> to permit access to
the Configuration bits and Device ID sections of the
configuration memory space.
Memory maps for the PIC24FJ256GB110 family of
devices are shown in Figure 3-1.
FIGURE 3-1:
PROGRAM SPACE MEMORY MAP FOR PIC24FJ256GB110 FAMILY DEVICES
PIC24FJ64GB1XX
GOTO Instruction
Reset Address
Interrupt Vector Table
Reserved
Alternate Vector Table
User Flash
Program Memory
(22K instructions)
Flash Config Words
PIC24FJ128GB1XX
GOTO Instruction
Reset Address
Interrupt Vector Table
Reserved
Alternate Vector Table
User Flash
Program Memory
(44K instructions)
Flash Config Words
PIC24FJ192GB1XX
GOTO Instruction
Reset Address
Interrupt Vector Table
Reserved
Alternate Vector Table
User Flash
Program Memory
(67K instructions)
PIC24FJ256GB1XX
GOTO Instruction
Reset Address
Interrupt Vector Table
Reserved
Alternate Vector Table
000000h
000002h
000004h
0000FEh
000100h
000104h
0001FEh
000200h
User Flash
Program Memory
(87K instructions)
00ABFEh
00AC00h
0157FEh
015800h
Unimplemented
Read ‘0’
Unimplemented
Read ‘0’
Flash Config Words
Unimplemented
Read ‘0’
Flash Config Words
020BFEh
020C00h
02ABFEh
02AC00h
Unimplemented
Read ‘0’
Reserved
Reserved
Reserved
Reserved
7FFFFFh
800000h
Device Config Registers
Device Config Registers
Reserved
Reserved
DEVID (2)
DEVID (2)
Note: Memory areas are not shown to scale.
Device Config Registers
Reserved
DEVID (2)
Device Config Registers
F7FFFEh
F80000h
F8000Eh
F80010h
Reserved
DEVID (2)
FEFFFEh
FF0000h
FFFFFFh
© 2008 Microchip Technology Inc.
Preliminary
DS39897B-page 31