PIC24FJ256GB110-I Datasheet, PDF (203/328 Pages) Microchip Technology – 64/80/100-Pin, 16-Bit Flash Microcontrollers with USB On-The-Go (OTG)

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17.3 USB Interrupts
The USB OTG module has many conditions that can
be configured to cause an interrupt. All interrupt
sources use the same interrupt vector.
Figure 17-4 shows the interrupt logic for the USB mod-
ule. There are two layers of interrupt registers in the
USB module. The top level consists of overall USB sta-
tus interrupts; these are enabled and flagged in the
U1IE and U1IR registers, respectively. The second
level consists of USB error conditions, which are
enabled and flagged in the U1EIR and U1EIE registers.
An interrupt condition in any of these triggers a USB
Error Interrupt Flag (UERRIF) in the top level.
17.3.1 CLEARING USB OTG INTERRUPTS
Unlike device level interrupts, the USB OTG interrupt
status flags are not freely writable in software. All USB
OTG flag bits are implemented as hardware set only
bits. Additionally, these bits can only be cleared in soft-
ware by writing a ‘1’ to their locations (i.e., performing
a MOV type instruction). Writing a ‘0’ to a flag bit (i.e., a
BCLR instruction) has no effect.
Note:
Throughout this data sheet, a bit that can
only be cleared by writing a ‘1’ to its loca-
tion is referred to as “Write 1 to clear”. In
register descriptions, this function is
indicated by the descriptor “K”.
FIGURE 17-4:
USB OTG INTERRUPT FUNNEL
Top Level (USB Status) Interrupts
STALLIF
STALLIE
ATTACHIF
ATTACHIE
RESUMEIF
RESUMEIE
IDLEIF
IDLEIE
Second Level (USB Error) Interrupts
BTSEF
BTSEE
DMAEF
DMAEE
TRNIF
TRNIE
SOFIF
SOFIE
URSTIF (DETACHIF)
URSTIE (DETACHIE)
BTOEF
BTOEE
DFN8EF
DFN8EE
CRC16EF
CRC16EE
CRC5EF (EOFEF)
CRC5EE (EOFEE)
PIDEF
PIDEE
(UERRIF)
UERRIE
IDIF
IDIE
T1MSECIF
TIMSECIE
LSTATEIF
LSTATEIE
ACTVIF
ACTVIE
SESVDIF
SESVDIE
SESENDIF
SESENDIE
Top Level (USB OTG) Interrupts
VBUSVDIF
VBUSVDIE
Set USB1IF
© 2008 Microchip Technology Inc.
Preliminary
DS39897B-page 201