PIC24FJ256GB110-I Datasheet, PDF (112/328 Pages) Microchip Technology – 64/80/100-Pin, 16-Bit Flash Microcontrollers with USB On-The-Go (OTG)

PIC24FJ256GB110 FAMILY
7.1 CPU Clocking Scheme
The system clock source can be provided by one of
four sources:
• Primary Oscillator (POSC) on the OSCI and
OSCO pins
• Secondary Oscillator (SOSC) on the SOSCI and
SOSCO pins
• Fast Internal RC (FRC) Oscillator
• Low-Power Internal RC (LPRC) Oscillator
The primary oscillator and FRC sources have the
option of using the internal USB PLL block, which
generates both the USB module clock and a separate
system clock from the 96 MHZ PLL. Refer to
Section 7.5 “Oscillator Modes and USB Operation”
for additional information.
The internal FRC provides an 8 MHz clock source. It
can optionally be reduced by the programmable clock
divider to provide a range of system clock frequencies.
The selected clock source generates the processor
and peripheral clock sources. The processor clock
source is divided by two to produce the internal instruc-
tion cycle clock, FCY. In this document, the instruction
cycle clock is also denoted by FOSC/2. The internal
instruction cycle clock, FOSC/2, can be provided on the
OSCO I/O pin for some operating modes of the primary
oscillator.
7.2 Initial Configuration on POR
The oscillator source (and operating mode) that is
used at a device Power-on Reset event is selected
using Configuration bit settings. The oscillator Config-
uration bit settings are located in the Configuration
registers in the program memory (refer to
Section 25.1 “Configuration Bits” for further
details). The Primary Oscillator Configuration bits,
POSCMD1:POSCMD0 (Configuration Word 2<1:0>),
and the Initial Oscillator Select Configuration bits,
FNOSC2:FNOSC0 (Configuration Word 2<10:8>),
select the oscillator source that is used at a Power-on
Reset. The FRC primary oscillator with postscaler
(FRCDIV) is the default (unprogrammed) selection.
The secondary oscillator, or one of the internal
oscillators, may be chosen by programming these bit
locations.
The Configuration bits allow users to choose between
the various clock modes, shown in Table 7-1.
7.2.1
CLOCK SWITCHING MODE
CONFIGURATION BITS
The FCKSM Configuration bits (Configuration
Word 2<7:6>) are used to jointly configure device clock
switching and the Fail-Safe Clock Monitor (FSCM).
Clock switching is enabled only when FCKSM1 is
programmed (‘0’). The FSCM is enabled only when
FCKSM1:FCKSM0 are both programmed (‘00’).
TABLE 7-1: CONFIGURATION BIT VALUES FOR CLOCK SELECTION
Oscillator Mode
Oscillator Source
POSCMD1:
POSCMD0
Fast RC Oscillator with Postscaler
Internal
11
(FRCDIV)
(Reserved)
Internal
xx
Low-Power RC Oscillator (LPRC)
Internal
11
Secondary (Timer1) Oscillator
Secondary
11
(SOSC)
Primary Oscillator (XT) with PLL
Primary
01
Module (XTPLL)
Primary Oscillator (EC) with PLL
Primary
00
Module (ECPLL)
Primary Oscillator (HS)
Primary
10
Primary Oscillator (XT)
Primary
01
Primary Oscillator (EC)
Primary
00
Fast RC Oscillator with PLL Module
Internal
11
(FRCPLL)
Fast RC Oscillator (FRC)
Internal
11
Note 1: OSCO pin function is determined by the OSCIOFCN Configuration bit.
2: This is the default oscillator mode for an unprogrammed (erased) device.
FNOSC2:
FNOSC0
111
110
101
100
011
011
010
010
010
001
000
Note
1, 2
1
1
1
1
1
DS39897B-page 110
Preliminary
© 2008 Microchip Technology Inc.