PIC24FJ256GB110-I Datasheet, PDF (126/328 Pages) Microchip Technology – 64/80/100-Pin, 16-Bit Flash Microcontrollers with USB On-The-Go (OTG)

PIC24FJ256GB110 FAMILY
9.4.3.1 Input Mapping
The inputs of the peripheral pin select options are
mapped on the basis of the peripheral; that is, a control
register associated with a peripheral dictates the pin it
will be mapped to. The RPINRx registers are used to
configure peripheral input mapping (see Register 9-1
through Register 9-21). Each register contains two sets
of 6-bit fields, with each set associated with one of the
pin selectable peripherals. Programming a given
peripheral’s bit field with an appropriate 6-bit value
maps the RPn pin with that value to that peripheral. For
any given device, the valid range of values for any of
the bit fields corresponds to the maximum number of
peripheral pin selections supported by the device.
TABLE 9-1: SELECTABLE INPUT SOURCES (MAPS INPUT TO FUNCTION)⁽¹⁾
Input Name
Function Name
Register
Function Mapping
Bits
External Interrupt 1
External Interrupt 2
External Interrupt 3
External Interrupt 4
Input Capture 1
Input Capture 2
Input Capture 3
Input Capture 4
Input Capture 5
Input Capture 6
Input Capture 7
Input Capture 8
Input Capture 9
Output Compare Fault A
Output Compare Fault B
SPI1 Clock Input
SPI1 Data Input
SPI1 Slave Select Input
SPI2 Clock Input
SPI2 Data Input
SPI2 Slave Select Input
SPI3 Clock Input
SPI3 Data Input
SPI3 Slave Select Input
Timer1 External Clock
Timer2 External Clock
Timer3 External Clock
Timer4 External Clock
Timer5 External Clock
INT1
INT2
INT3
INT4
IC1
IC2
IC3
IC4
IC5
IC6
IC7
IC8
IC9
OCFA
OCFB
SCK1IN
SDI1
SS1IN
SCK2IN
SDI2
SS2IN
SCK3IN
SDI3
SS3IN
T1CK
T2CK
T3CK
T4CK
T5CK
RPINR0
RPINR1
RPINR1
RPINR2
RPINR7
RPINR7
RPINR8
RPINR8
RPINR9
RPINR9
RPINR10
RPINR10
RPINR15
RPINR11
RPINR11
RPINR20
RPINR20
RPINR21
RPINR22
RPINR22
RPINR23
RPINR23
RPINR28
RPINR29
RPINR2
RPINR3
RPINR3
RPINR4
RPINR4
INT1R5:INT1R0
INT2R5:INT2R0
INT3R5:INT3R0
INT4R5:INT4R0
IC1R5:IC1R0
IC2R5:IC2R0
IC3R5:IC3R0
IC4R5:IC4R0
IC5R5:IC5R0
IC6R5:IC6R0
IC7R5:IC7R0
IC8R5:IC8R0
IC9R5:IC9R0
OCFAR5:OCFAR0
OCFBR5:OCFBR0
SCK1R5:SCK1R0
SDI1R5:SDI1R0
SS1R5:SS1R0
SCK2R5:SCK2R0
SDI2R5:SDI2R0
SS2R5:SS2R0
SCK3R5:SCK3R0
SDI3R5:SDI3R0
SS3R5:SS3R0
T1CKR5:T1CKR0
T2CKR5:T2CKR0
T3CKR5:T3CKR0
T4CKR5:T4CKR0
T5CKR5:T5CKR0
UART1 Clear To Send
UART1 Receive
U1CTS
U1RX
RPINR18
RPINR18
U1CTSR5:U1CTSR0
U1RXR5:U1RXR0
UART2 Clear To Send
UART2 Receive
U2CTS
U2RX
RPINR19
RPINR19
U2CTSR5:U2CTSR0
U2RXR5:U2RXR0
UART3 Clear To Send
UART3 Receive
U3CTS
U3RX
RPINR21
RPINR17
U3CTSR5:U3CTSR0
U3RXR5:U3RXR0
UART4 Clear To Send
U4CTS
RPINR27
UART4 Receive
U4RX
RPINR27
Note 1: Unless otherwise noted, all inputs use the Schmitt Trigger input buffers.
U4CTSR5:U4CTSR0
U4RXR5:U4RXR0
DS39897B-page 124
Preliminary
© 2008 Microchip Technology Inc.