71M6541D Datasheet, PDF (82/166 Pages) Maxim Integrated Products – 0.1% Accuracy Over 2000:1 Current Range Energy Meter ICs

71M6541D/F/G and 71M6542F/G Data Sheet
Transitions from both LCD and SLP mode to BRN mode can be initiated by the following events:
• Wake-up timer timeout.
• Pushbutton (PB) is activated.
• A rising edge on SEGDIO4, SEGDIO52 (71M6542F/G only) or SEGDIO55.
• Activity on the RX or OPT_RX pins.
The MPU has access to a variety of registers that signal the event that caused the wake up. See 3.4
Wake Up Behavior for details.
Table 67 shows the circuit functions available in each operating mode.
Table 67: Available Circuit Functions
System Power
Battery Power
Circuit Function
CE (Computation Engine)
FIR
ADC, VREF
PLL
Battery Measurement
Temperature sensor
Max MPU clock rate
MPU_DIV clk. divider
ICE
DIO Pins
Watchdog Timer
LCD
LCD Boost
EEPROM Interface (2-wire)
EEPROM Interface (3-wire)
UART (full speed)
Optical TX modulation
Flash Read
Flash Page Erase
Flash Write
RAM Read and Write
Wakeup Timer
OSC and RTC
DRAM data preservation
NV RAM data preservation
MSN (Mission Mode)
PLL_FAST=1 PLL_FAST=0
Yes
Yes
Yes
Yes
Yes
Yes
4.92MHz
(from PLL)
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
38.4kHz
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
1.57MHz
(from PLL)
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
38.9kHz
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
BRN (Brownout Mode)
PLL_FAST=1 PLL_FAST=0
Note 1
--
--
Yes
Yes
Yes
4.92MHz
(from PLL)
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
38.4kHz
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Note 1
--
--
Yes
Yes
Yes
1.57MHz
(from PLL)
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
38.9kHz
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
LCD
--²
--
--
Boost²
--
Yes
--
--
--
--
--
Yes
Yes
--
--
--
--
--
--
--
--
Yes
Yes
--
Yes
SLEEP
--
--
--
--
--
Yes
--
--
--
--
--
--
--
--
--
--
--
--
--
--
Yes
Yes
--
Yes
Notes:
1. The CE is active in BRN mode, but ADC data is inaccurate. The MPU should halt the CE to conserve power (CE_E = 0,
I/O RAM 0x2106[0]).
2. “--“ indicates that the corresponding circuit is not active
3. “Boost” implies that the LCD boost circuit is active (i.e., LCD_VMODE[1:0] = 10 (I/O RAM 0x2401[7:6]). The LCD boost
circuit requires a clock from the PLL to function. Thus, the PLL is automatically kept active if LCD boost is active while in
LCD mode, otherwise the PLL is de-activated.