71M6541D Datasheet, PDF (115/166 Pages) Maxim Integrated Products – 0.1% Accuracy Over 2000:1 Current Range Energy Meter ICs

Name
FLSH_ERASE[7:0]
FLSH_MEEN
FLSH_PEND
FLSH_PGADR[5:0]
FLSH_PSTWR
FLSH_PWE
FLSH_RDE
FLSH_UNLOCK[3:0]
FLSH_WRE
Location
SFR 94[7:0]
SFR B2[1]
SFR B2[3]
SFR B7[7:2]
SFR B2[2]
SFR B2[0]
2702[2]
2702[7:4]
2702[1]
71M6541D/F/G and 71M6542F/G Data Sheet
Rst Wk Dir Description
00
Flash Erase Initiate
FLSH_ERASE is used to initiate either the Flash Mass Erase cycle or the Flash
Page Erase cycle. Specific patterns are expected for FLSH_ERASE in order
to initiate the appropriate Erase cycle.
W
(default = 0x00).
0x55 = Initiate Flash Page Erase cycle. Must be proceeded by a write to
FLSH_PGADR[5:0] (SFR 0xB7[7:2]).
0xAA = Initiate Flash Mass Erase cycle. Must be proceeded by a write to
FLSH_MEEN and the ICE port must be enabled.
Any other pattern written to FLSH_ERASE has no effect.
00
Mass Erase Enable
W
0 = Mass Erase disabled (default).
1 = Mass Erase enabled.
Must be re-written for each new Mass Erase cycle.
00
R
Indicates that a timed flash write is pending. If another flash write is attempted,
it is ignored.
00
Flash Page Erase Address
W
FLSH_PGADR[5:0] – Flash Page Address (page 0 thru 63) that is erased during
the Page Erase cycle. (default = 0x00).
Must be re-written for each new Page Erase cycle.
Enables timed flash writes. When 1, and if CE_E = 1, flash write requests are
0
0
R/W
stored in a one-element deep FIFO and are executed when CE_BUSY falls.
FLSH_PEND can be read to determine the status of the FIFO. If
FLSH_PSTWR = 0 or if CE_E = 0, flash writes are immediate.
Program Write Enable
0 = MOVX commands refer to External RAM Space, normal operation (default).
0 0 R/W 1 = MOVX @DPTR,A moves A to External Program Space (Flash) @ DPTR.
This bit is automatically reset after each byte written to flash. Writes to this bit
are inhibited when interrupts are enabled.
––
R
Indicates that the flash may be read by ICE or SPI slave. FLSH_RDE =
(!SECURE)
0
0
R/W
Must be a ‘2’ to enable any flash modification. See the description of Flash
security for more details.
– – R Indicates that the flash may be written through ICE or SPI slave ports.