71M6541D Datasheet, PDF (78/166 Pages) Maxim Integrated Products – 0.1% Accuracy Over 2000:1 Current Range Energy Meter ICs

71M6541D/F/G and 71M6542F/G Data Sheet
SFM details
The following occurs upon entering SFM.
• The CE is disabled.
• The MPU is halted. Once the MPU is halted it can only be restarted with a reset. This reset can be
accomplished with the RESET pin, a watchdog reset, or by cycling power (without battery at the
VBAT pin).
• The Flash control logic is reset in case the MPU was in the middle of a Flash write operation or Erase
cycle.
• Mass erase is invoked if specified in the SFMM register, I/O RAM 0x2080 (see Invoking SFM, above).
The SECURE bit (SFR 0xB2[6]) is cleared at the end of this and all Mass Erase cycles.
• All SPI read and write operations now refer to Flash instead of XRAM space.
The SPI host can access the current state of the pending multi-cycle Flash access by performing a 4-byte
SPI write of any address and checking the status field.
All SPI write operations in SFM mode must be 6-byte write transaction that writes two bytes to an even
address. The write transactions must contain a command byte of the form 0xxx xxxx. Auto incrementing
is disabled for write operations.
SPI read transactions can make use of auto increment and may access single bytes. The command byte
must always be of the form 1xxx xxxx in SFM read transactions.
SPI commands in SFM
Interrupts are not generated in SFM since the MPU is halted. The format of the commands is described in
the SPI Transactions description on Page 73.
2.5.11 Hardware Watchdog Timer
An independent, robust, fixed-duration, watchdog timer (WDT) is included in the 71M6541D/F/G and
71M6542F/G. It uses the RTC crystal oscillator as its time base and must be refreshed by the MPU
firmware at least every 1.5 seconds. When not refreshed on time, the WDT overflows and the part is
reset as if the RESET pin were pulled high, except that the I/O RAM bits are in the same state as after a
wake-up from SLP or LCD modes (see the I/O RAM description in 5.2 I/O RAM Map – Alphabetical Order
for a list of I/O RAM bit states after RESET and wake-up). After 4100 CK32 cycles (or 125 ms) following
the WDT overflow, the MPU is launched from program address 0x0000.
The watchdog timer is also reset when the internal signal WAKE=0 (see 3.4 Wake Up Behavior).
For details, see 3.3.4 Watchdog Timer Reset.
2.5.12 Test Ports (TMUXOUT and TMUX2OUT Pins)
Two independent multiplexers allow the selection of internal analog and digital signals for the TMUXOUT
and TMUX2OUT pins. These pins are multiplexed with the SEG47 and SEG46 function. In order to function
as test pins, LCD_MAP[46] (I/O RAM 0x2406[6]) and LCD_MAP[47] (I/O RAM 0x2406[7]) must be 0.
One of the digital or analog signals listed in
Table 65 can be selected to be output on the TMUXOUT pin. The function of the multiplexer is controlled
with the I/O RAM register TMUX[5:0] (I/O RAM 0x2502[5:0], as shown in
Table 65.
One of the digital or analog signals listed in Table 66 can be selected to be output on the TMUX2OUT pin.
The function of the multiplexer is controlled with the I/O RAM register TMUX2[4:0] (I/O RAM 0x2503[4:0]), as
shown in Table 66.
The TMUX[5:0] and TMUX2[4:0] I/O RAM locations are non-volatile and their contents are preserved
by battery power and across resets.