71M6541D Datasheet, PDF (122/166 Pages) Maxim Integrated Products – 0.1% Accuracy Over 2000:1 Current Range Energy Meter ICs

71M6541D/F/G and 71M6542F/G Data Sheet
Name
RTM_E
RTM0[9:8]
RTM0[7:0]
RTM1[7:0]
RTM2[7:0]
RTM3[7:0]
SECURE
SLEEP
SPI_CMD[7:0]
SPI_E
SPI_SAFE
SPI_STAT[7:0]
STEMP[10:3]
STEMP[2:0]
SUM_SAMPS[12:8]
SUM_SAMPS[7:0]
TBYTE_BUSY
Location
2106[1]
210D[1:0]
210E[7:0]
210F[7:0]
2110[7:0]
2111[7:0]
SFR B2[6]
28B2[7]
SFR FD[7:0]
270C[4]
270C[3]
2708[7:0]
2881[7:0]
2882[7:5]
2107[4:0]
2108[7:0]
28A0[3]
Rst Wk Dir Description
0 0 R/W Real Time Monitor enable. When 0, the RTM output is low.
00
0
0
0
0
0
0
Four RTM probes. Before each CE code pass, the values of these registers
R/W
are serially output on the RTM pin. The RTM registers are ignored when
RTM_E = 0. Note that RTM0 is 10 bits wide. The others assume the upper
two bits are 00.
00
Inhibits erasure of page 0 and flash addresses above the beginning of CE code
0 0 R/W as defined by CE_LCTN[5:0]. Also inhibits the read of flash via the SPI and ICE
port.
00
Puts the part to SLP mode. Ignored if system power is present. The part
W wakes when the Wake timer times out, when push button is pushed, or when
system power returns.
– – R SPI command register for the 8-bit command from the bus master.
1
1
R/W
SPI port enable. Enables SPI interface on pins SEGDIO36 – SEGDIO39.
Requires that LCD_MAP[36-39] = 0.
0
0
R/W
Limits SPI writes to SPI_CMD and a 16-byte region in DRAM. No other
writes are permitted.
00
SPI_STAT contains the status results from the previous SPI transaction.
Bit 7: Ready error: The 71M654x was not ready to read or write as directed
by the previous command.
Bit 6: Read data parity: This bit is the parity of all bytes read from the
71M654x in the previous command. Does not include the SPI_STAT byte.
Bit 5: Write data parity: This bit is the overall parity of the bytes written to the
R 71M654x in the previous command. It includes CMD and ADDR bytes.
Bit 4-2: Bottom 3 bits of the byte count. Does not include ADDR and CMD
bytes. One, two, and three byte
instructions return 111.
Bit 1: SPI FLASH mode: This bit is zero when the TEST pin is zero.
Bit 0: SPI FLASH mode ready: Used in SPI FLASH mode. Indicates that the
flash is ready to receive another write instruction.
––
––
R
R
The result of the temperature measurement.
0
0
R/W
The number of multiplexer cycles per XFER_BUSY interrupt. Maximum value
is 8191 cycles.
00
Indicates that hardware is still writing the 0x28A0 byte. Additional writes to
R this byte are locked out while it is one. Write duration could be as long as
6ms.