71M6541D Datasheet, PDF (44/166 Pages) Maxim Integrated Products – 0.1% Accuracy Over 2000:1 Current Range Energy Meter ICs

71M6541D/F/G and 71M6542F/G Data Sheet
External MPU Interrupts
The seven external interrupts are the interrupts external to the 80515 core, i.e., signals that originate in
other parts of the 71M654x, for example the CE, DIO, RTC, or EEPROM interface.
The external interrupts are connected as shown in Table 32. The polarity of interrupts 2 and 3 is
programmable in the MPU via the I3FR and I2FR bits in T2CON (SFR 0xC8). Interrupts 2 and 3 should be
programmed for falling sensitivity (I3FR = I2FR = 0). The generic 8051 MPU literature states that interrupts 4
through 6 are defined as rising-edge sensitive. Thus, the hardware signals attached to interrupts 5
and 6 are inverted to achieve the edge polarity shown in Table 32.
External
Interrupt
0
1
2
3
4
5
6
Table 32: External MPU Interrupts
Connection
Polarity
Digital I/O
Digital I/O
CE_PULSE
CE_BUSY
VSTAT (VSTAT[2:0] changed)
EEPROM busy (falling), SPI (rising)
XFER_BUSY (falling), RTC_1SEC, RTC_1MIN, RTC_T
see 2.5.8
see 2.5.8
rising
falling
rising
falling
Flag Reset
automatic
automatic
automatic
automatic
automatic
automatic
manual
External interrupt 0 and 1 can be mapped to pins on the device using DIO resource maps. See 2.5.8
Digital I/O for more information.
SFR enable bits must be set to permit any of these interrupts to occur. Likewise, each interrupt has its own
flag bit, which is set by the interrupt hardware, and reset by the MPU interrupt handler. XFER_BUSY,
RTC_1SEC, RTC_1MIN, RTC_T, SPI, PLLRISE and PLLFALL have their own enable and flag bits in
addition to the interrupt 6, 4 and enable and flag bits (see Table 33: Interrupt Enable and Flag Bits).
IE0 through IEX6 are cleared automatically when the hardware vectors to the interrupt handler.
The other flags, IE_XFER through IE_VPULSE, are cleared by writing a zero to them.
Since these bits are in an SFR bit addressable byte, common practice would be to clear them
with a bit operation, but this must be avoided. The hardware implements bit operations as a
byte wide read-modify-write hardware macro. If an interrupt occurs after the read, but before
the write, its flag cleared unintentionally.
The proper way to clear the flag bits is to write a byte mask consisting of all ones except for a
zero in the location of the bit to be cleared. The flag bits are configured in hardware to ignore
ones written to them.
Table 33: Interrupt Enable and Flag Bits
Interrupt Enable
Name
Location
EX0
SFR 0xA8[[0]
EX1
SFR 0xA8[2]
EX2
SFR 0xB8[1]
EX3
SFR 0xB8[2]
EX4
SFR 0xB8[3]
EX5
SFR 0xB8[4]
EX6
SFR 0xB8[5]
EX_XFER
EX_RTC1S
EX_RTC1M
EX_RTCT
0x2700[0]
0x2700[1]
0x2700[2]
0x2700[4]
Interrupt Flag
Name
Location
IE0
SFR 0x88[1]
IE1
IEX2
IEX3
SFR 0x88[3]
SFR 0xC0[1]
SFR 0xC0[2]
IEX4
IEX5
IEX6
SFR 0xC0[3]
SFR 0xC0[4]
SFR 0xC0[5]
IE_XFER
IE_RTC1S
IE_RTC1M
IE_RTCT
SFR 0xE8[0]
SFR 0xE8[1]
SFR E0x8[2]
SFR 0xE8[4]
Interrupt Description
External interrupt 0
External interrupt 1
External interrupt 2
External interrupt 3
External interrupt 4
External interrupt 5
External interrupt 6
XFER_BUSY interrupt (int 6)
RTC_1SEC interrupt (int 6)
RTC_1MIN interrupt (int 6)
RTC_T alarm clock interrupt (int 6)