71M6541D Datasheet, PDF (63/166 Pages) Maxim Integrated Products – 0.1% Accuracy Over 2000:1 Current Range Energy Meter ICs

71M6541D/F/G and 71M6542F/G Data Sheet
2.5.8.3 Digital I/O for the 71M6542F/G
A total of 55 combined SEG/DIO pins are available for the 71M6542D/F. These pins can be categorized
as follows:
35 combined DIO/LCD segment pins:
o SEGDIO4…SEGDIO5 (2 pins)
o SEGDIO9…SEGDIO25 (17 pins)
o SEGDIO28…SEGDIO35 (8 pins)
o SEGDIO40…SEGDIO45 (6 pins)
o SEGDIO52…SEGDIO53 (2 pins)
15 combined DIO/LCD segment pins shared with other functions:
o SEGDIO0/WPULSE, SEGDIO1/VPULSE (2 pins)
o SEGDIO2/SDCK, SEGDIO3/SDATA (2 pins)
o SEGDIO6/XPULSE, SEGDIO7/YPULSE (2 pins)
o SEGDIO8/DI (1 pin)
o SEGDIO26/COM5, SEGDIO27/COM4 (2 pins)
o SEGDIO36/SPI_CSZ…SEGDIO39/SPI_CKI (4 pins)
o SEGDIO51/OPT_TX, SEGDIO55/OPT_RX (2 pins)
5 dedicated SEG segment pins are available:
o ICE Inteface pins: SEG48/E_RXTX, SEG49/E_TCLK, SEG50/E_RST (3 pins)
o Test Port pins: SEG46/TMUX2OUT, SEG47/TMUXOUT (2 pins)
There are four dedicated common segment outputs (COM0…COM3) plus the two additional shared common
segment outputs that are listed under combined SEG/DIO shared pins (SEGDIO26/COM5,
SEGDIO27/COM4).
Thus, in a configuration where none of these pins are used as DIOs, there can be up to 55 LCD segment
pins with 4 commons, or 53 LCD segment pins with 6 commons. And in a configuration where LCD
segment pins are not used, there can be up to 50 DIO pins.
Example: SEGDIO12 (see pin 32 in Table 52) is configured as a DIO output pin with a value of 1 (high) by
writing 0 to bit 4 of LCD_MAP[15:8], and writing 1 to both P3[4]and P3[0]. The same pin is configured as
an LCD driver by writing 1 to bit 4 of LCD_MAP[15:8]. The display information is written to bits 0 to 5 of
LCD_SEG12.
The configuration for pins SEGDIO16 to SEGDIO31 is shown in Table 53, the configuration for pins
SEGDIO32 to SEGDIO45 is shown in Table 54. SEG46 through SEG50 cannot be configured as DIO
pins. The configuration for pins SEGDIO51 to SEGDIO55 is shown in Table 55.
Table 52: Data/Direction Registers for SEGDIO0 to SEGDIO15 (71M6542F/G)
SEGDIO
Pin #
Configuration:
0 = DIO, 1 = LCD
SEG Data Register
DIO Data Register
Direction Register:
0 = input, 1 = output
Internal Resources
Configurable
(see Table 47)
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
45 44 43 42 41 39 38 37 36 35 34 33 32 31 30 29
0 123 4 56 7 01 2 34567
LCD_MAP[7:0] (I/O RAM 0x240B)
LCD_MAP[15:8] (I/O RAM 0x240A)
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
LCD_SEG0[5:0] to LCD_SEG15[5:0] (I/O RAM 0x2410[5:0] to 0x241F[5:0]
0 123 0 12 3 01 2 30123
P0 (SFR 0x80)
P1 (SFR 0x90)
P2 (SFR 0xA0)
P3 (SFR 0xB0)
4 567 4 56 7 45 6 74567
P0 (SFR 0x80)
P1 (SFR 0x0)
P2 (SFR 0xA0)
P3 (SFR 0xB0)
– –YY Y YY YYY Y Y– – – –