71M6541D Datasheet, PDF (72/166 Pages) Maxim Integrated Products – 0.1% Accuracy Over 2000:1 Current Range Energy Meter ICs

71M6541D/F/G and 71M6542F/G Data Sheet
4
RD
W Indicates that EEDATA (SFR 0x9E) is to be filled with data from EEPROM.
Specifies the number of clocks to be issued. Allowed values are 0
through 8. If RD=1, CNT bits of data are read MSB first, and right
3:0 CNT[3:0] W justified into the low order bits of EEDATA. If RD=0, CNT bits are sent
MSB first to the EEPROM, shifted out of the MSB of EEDATA. If
CNT[3:0] is zero, SDATA simply obeys the HiZ bit.
The timing diagrams in Figure 22 through Figure 26 describe the 3-wire EEPROM interface behavior. All
commands begin when the EECTRL (SFR 0x9F) register is written. Transactions start by first raising the
DIO pin that is connected to CS. Multiple 8-bit or less commands such as those shown in Figure 22
through Figure 26 are then sent via EECTRL and EEDATA.
When the transaction is finished, CS must be lowered. At the end of a Read transaction, the EEPROM is
driving SDATA, but transitions to Hi-Z (high impedance) when CS falls. The firmware should then
immediately issue a write command with CNT=0 and HiZ=0 to take control of SDATA and force it to a
low-Z state.
EECTRL Byte Written
Write -- No HiZ
SCLK (output)
CNT Cycles (6 shown)
INT5
SDATA (output)
D7
D6
D5
D4
D3
D2
SDATA output Z
(LoZ)
BUSY (bit)
Figure 22: 3-wire Interface. Write Command, HiZ=0.
EECTRL Byte Written
Write -- With HiZ
SCLK (output)
CNT Cycles (6 shown)
INT5
SDATA (output)
D7
D6
D5
D4
D3
D2
SDATA output Z
(LoZ)
(HiZ)
BUSY (bit)
Figure 23: 3-wire Interface. Write Command, HiZ=1
EECTRL Byte Written
READ
SCLK (output)
CNT Cycles (8 shown)
INT5
SDATA (input)
D7
D6
D5
D4
D3
D2
D1
D0
SDATA output Z
(HiZ)
BUSY (bit)
Figure 24: 3-wire Interface. Read Command.