71M6541D Datasheet, PDF (128/166 Pages) Maxim Integrated Products – 0.1% Accuracy Over 2000:1 Current Range Energy Meter ICs

71M6541D/F/G and 71M6542F/G Data Sheet
status flags for the preceding CE code pass (CE_BUSY interrupt). The significance of the bits in
CESTATUS is shown in Table 81.
CESTATUS
bit
31:4
3
2
1
0
Table 81: CESTATUS (CE RAM 0x80) Bit Definitions
Name
Description
Not Used
F0
Not Used
SAG_B
SAG_A
These unused bits are always zero.
F0 is a square wave at the exact fundamental input frequency.
This unused bit is always zero.
Normally zero. Becomes one when VB remains below SAG_THR for
SAG_CNT samples. Does not return to zero until VB rises above
SAG_THR.
Normally zero. Becomes one when VA remains below SAG_THR for
SAG_CNT samples. Does not return to zero until VA rises above
SAG_THR.
The CE is initialized by the MPU using CECONFIG (Table 82). This register contains in packed form
SAG_CNT, FREQSEL[1:0], EXT_PULSE, PULSE_SLOW and PULSE_FAST. The CECONFIG bit definitions are
given in Table 83.
Table 82: CECONFIG Register
CE
Address
0x20
Name
CECONFIG
Data
0x0030DB00¹
0x00B0DB00²
Description
See description of the CECONFIG bits in
Table 83.
1. Default for CE41A01 (71M6541D/F/G or CE41A04 (71M6542F/G) CE code for use with local
sensors.
2. Default for CE41B016201 and CE41B016601 codes that support the 71M6x01 remote
sensors.
Table 83: CECONFIG (CE RAM 0x20) Bit Definitions
CECONFIG
bit
23
Name
Reserved
22
EXT_TEMP
21
EDGE_INT
20
SAG_INT
19:8
SAG_CNT
Default Description
0
0
1
1
252
(0xFC)
When this bit is set, control of temperature compensation is
enabled for the 71M6x01 Isolated Sensor Interface.
When 1, the MPU controls temperature compensation via the
GAIN_ADJn registers (CE RAM 0x40-0x42), when 0, the CE is in
control.
When 1, XPULSE produces a pulse for each zero-crossing of
the mains phase selected by FREQSEL[1:0] , which can be used
to interrupt the MPU.
When 1, activates YPULSE output when a sag condition is
detected.
The number of consecutive voltage samples below SAG_THR
(CE RAM 0x24) before a sag alarm is declared. The default value
is equivalent to 100 ms.
FREQSEL[1:0] selects the phase to be used for the frequency
monitor, sag detection, and for the zero crossing counter
(MAINEDGE_X, CE RAM 0x83).
7:6 FREQSEL[1:0] 0
FREQ SEL[1:0]
Phase Selected
0
0
0
1
1
X
*71M6542F/G only
A
B*
Not allowed