MAX1329 Datasheet, PDF (71/78 Pages) Maxim Integrated Products – 12-/16-Bit DASs with ADC, DACs, DPIOs, APIOs, Reference, Voltage Monitors, and Temp Sensor

12-/16-Bit DASs with ADC, DACs, DPIOs, APIOs,
Reference, Voltage Monitors, and Temp Sensor
Charge-Pump Component Selection
Optimize the charge-pump circuit for size, quiescent
current, and output ripple by properly selecting the
operating frequency and capacitors C_DVDD, C_FLY, and
C_AVDD (Table 32). The charge pump is capable of pro-
viding a maximum of 25mA including what is used
internally. If less than 25mA is required, smaller capaci-
tor values can be utilized.
For lowest ripple, select 117kHz operation (CPDIV<1:0>
= 00 and OSCE = 1 when using the internal oscillator). In
addition, increasing C_AVDD relative to C_FLY further
reduces ripple. For highest efficiency, select 14.6kHz
operation (CPDIV<1:0> = 11 and OSCE = 1 when using
the internal oscillator) and select the largest practical
values for C_AVDD and C_FLY while maintaining at least a
30-to-1 ratio. For smallest size, select 117kHz operation.
See Table 32 for some suggested values and resulting
ripple for 25mA load current. See Figure 34 for load cur-
rent vs. flying capacitor value when optimizing for other
load currents.
Note that the capacitors must have low ESR to main-
tain low ripple. The C_FLY flying capacitor ESR needs
to be < 0.1Ω; and the C_AVDD and C_DVDD filter capaci-
tor ESR needs to be < 0.3Ω. The C_FLY flying capacitor
can easily be a ceramic capacitor; and the C_AVDD and
C_DVDD filter capacitor can be a low-ESR tantalum or
may need to be a combination of a small ceramic and a
larger tantalum capacitor.
When DV_DD is lower than AV_DD, the charge pump always
operates in voltage-doubler mode. It regulates the output
voltage using a pulse-width-modulation (PWM) scheme.
Using a PWM scheme ensures that the charge pump is
synchronous with the internal ADC preventing corruption
of the conversion results.
Table 32. External Component Selection
for 25mA Output Current and 2V_DVDD -
V_AVDD ≥ 0.4V (Figure 25)
CHARGE-PUMP ^ILOAD,
CLOCK (kHz) ^MAX
(mA)
25
14.4
12.5
25
28.8
12.5
25
57.6
12.5
25
115.2
12.5
C_FLY C_AVDD C_DVDD RIPPLE
(µF) (µF) (µF) (mV)
1.7 55.6 17.4
32
0.9 27.8 8.7
0.9 27.8 8.7
32
0.4 13.9 4.3
0.4 13.9 4.3
32
0.2
6.9
2.2
0.2
6.9
2.2
32
0.1
3.5
1.1
Operating the Analog Switches
The MAX1329/MAX1330 include two single-pole double-
throw (SPDT) and three single-pole single-throw (SPST)
analog switches. The two SPDT analog switches are
uncommitted and the three SPST analog switches are
connected between the DAC buffer or op amp outputs
and the inverting inputs.
The analog switches can be controlled using the Switch
Control register or any of the DPIOs. See the DPIO
Control and DPIO Setup registers to program the
DPIOs. The DPIOs should be used when direct control
is critical such as synchronizing with another event or if
the SPI bus bandwidth is not sufficient for the intended
application. The register bit for the analog switch is log-
ically OR’d with DPIOs enabled to control that switch.
The SPDT1 and SPDT2 analog switches can be operat-
ed as a SPDT or as a double-pole single-throw (DPST).
In the DPST mode, both switches can be opened or
closed together. This is useful when connecting two
external nodes to a common point. If a lower on-resis-
tance is required, NO_ and NC_ can be connected
together externally and be used as a SPST analog
switch with half the on-resistance.
The SPST analog switches are intended to be used to
set the DAC buffers and op amps to unity gain internal-
ly by software control. When the DAC buffers and op
amps are used as transimpedance amplifiers, the SPST
analog switches can be used to short the external tran-
simpedance resistor during high current periods to
keep the amplifier output in compliance.
CHARGE-PUMP LOAD CURRENT
vs. FLYING CAPACITOR VALUE
50
f_CP = 115.2kHz
45
40
f_CP = 57.6kHz
35
30
25
f_CP = 28.8kHz
20
15
10
f_CP = 14.4kHz
5
0
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
C_FLY (µF)
Figure 34. Load Current vs. CFLY Value for 2V_DVDD - V_AVDD ≥ 0.4V
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