MAX1329 Datasheet, PDF (57/78 Pages) Maxim Integrated Products – 12-/16-Bit DASs with ADC, DACs, DPIOs, APIOs, Reference, Voltage Monitors, and Temp Sensor

12-/16-Bit DASs with ADC, DACs, DPIOs, APIOs,
Reference, Voltage Monitors, and Temp Sensor
Table 29. SPDT2 Switch Control Configuration
SPDT21
BIT
0
0
0
0
0
0
1
1
1
1
1
1
SPDT20
BIT
0
X
X
X
X
1
0
X
X
X
X
1
DPIO4
0
X
X
X
1
X
0
X
X
X
1
X
DPIO3
0
X
X
1
X
X
0
X
X
1
X
X
DPIO2
0
X
1
X
X
X
0
X
1
X
X
X
DPIO1
0
1
X
X
X
X
0
1
X
X
X
X
SPDT2 SWITCH STATE
SNO2-TO-SCM2 STATE SNC2-TO-SCM2 STATE
Open
Open
Closed
Closed
Closed
Closed
Closed
Closed
Closed
Closed
Closed
Closed
Open
Closed
Closed
Open
Closed
Open
Closed
Open
Closed
Open
Closed
Open
APIO Control Register
The Analog Programmable Input/Output (APIO) Control
register configures the modes of APIO1–APIO4.
APIO1–APIO4 I/O logic levels are referenced to AV_DD and
AGND (see Analog I/O in the Electrical Characteristics
table). APIO_ is configurable as a general-purpose input,
active-low wake-up input, general-purpose output, or seri-
al-interface, level-shifted buffered I/O.
AP_MD<1:0>: APIO_ Mode Configuration bits (default
= 00). AP_MD<1:0> configures the APIO_ mode
according to Table 30.
NAME
DEFAULT
MSB
AP4MD1
0
AP4MD0
0
AP3MD1
0
AP3MD0
0
AP2MD1
0
AP2MD0
0
AP1MD1
0
LSB
AP1MD0
0
Table 30. APIO_ Mode Bit Configuration
AP_MD1
0
0
1
1
AP_MD0
0
1
0
1
MODE
GPI
WUL
GPO
SPI
DESCRIPTION
Digital input. APIO_ logic level read from AP_LL register bit.
Digital input. A falling edge on APIO_ sets the OSCE bit to 1 enabling the oscillator.
Digital output. Set the APIO_ logic level by writing to the AP_LL register bit.
Digital input or output. The SPI mode functions differ for each APIO1–APIO4.
• APIO1 digital input. DOUT outputs the APIO1 logic level when CS is high, and
APIO1 is a GPI, when CS is low. Set the resistor pullup configuration with the
AP1PU bit.
• APIO2 digital output. APIO2 outputs the DIN logic level when CS is high and
becomes a GPO with the level set by AP2LL bit when CS is low.
• APIO3 digital output. APIO3 outputs the SCLK logic level when CS is high and
becomes a GPO with the level set by the AP3LL bit when CS is low.
• APIO4 digital output. APIO4 inverts and then outputs the CS logic level.
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