MAX1329 Datasheet, PDF (35/78 Pages) Maxim Integrated Products – 12-/16-Bit DASs with ADC, DACs, DPIOs, APIOs, Reference, Voltage Monitors, and Temp Sensor

12-/16-Bit DASs with ADC, DACs, DPIOs, APIOs,
Reference, Voltage Monitors, and Temp Sensor
CS
SCLK
DIN
X
0
1
0 AB D11 D10 D9 D 8 D 7 D6 D 5 D4 D 3 D 2 D1 D0 X X X X X X
XX
DAC
PREVIOUS OUTPUT
NEW OUTPUT
DPIO
X = DON'T CARE.
RISING EDGE TRIGGERED
Figure 16. Write to DACA (AB = 0) or DACB (AB = 1) Input Register Followed by a DPIO DACA or DACB Load
CS
SCLK
WRITE TO MAX1329/MAX1330 TO
ENABLE SPI MODE
WRITE THROUGH MAX1329/MAX1330 TO
APIO DEVICE
NORMAL WRITE TO MAX1329/MAX1330
DIN
D_N D_N-1 D_N-2 D_N-3 D₃ D₂ D₁ D ₀ E _N E _N-1 E _N-2 E _{N-3 X}
X
X
X
D₇ D₆ D₅ D₄ D₃ D₂ D₁ D₀
DOUT
E₃ E₂ E₁ E₀
APIO4
SET BY APIO CONTROL REGISTER
INVERTED CS
APIO3
SET BY APIO CONTROL REGISTER
APIO2
SET BY APIO CONTROL REGISTER
E _N E _N-1 E _N-2 E _N-3 X _{X X X}
APIO1
SET BY APIO CONTROL REGISTER
X = DON'T CARE.
Figure 17. Write to Program and Use APIO SPI Mode
E₃ E₂ E₁ E₀
SET TO GPO
SET TO GPO
SET TO GPI
The four conversion modes programmed by the
APD<1:0> and AUTO<2:0> bits in the ADC Control
register are: autoconvert, fast power-down, normal, and
burst modes. In normal and fast power-down modes,
single conversions are initiated with the ADC convert
command or by toggling a configured DPIO. In fast
power-down mode, the PGA and ADC power down
between conversions to reduce power. A minimum of
16 clock cycles is required to complete a conversion in
normal or fast power-down mode.
Burst mode is initiated with one ADC convert com-
mand and continuously converts on the same channel
sending the data directly to DOUT as long as there is
activity on SCLK and CS is low. Burst mode aborts
when CS goes high. In burst mode, SCLK directly
clocks the ADC. For best performance, synchronize
SCLK with the CLKIO clock (see Figure 18). A mini-
mum of 14 clock cycles is required to complete a con-
version in burst mode.
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