MAX1329 Datasheet, PDF(25/78 Page) Maxim Integrated Products – 12-/16-Bit DASs with ADC, DACs, DPIOs, APIOs, Reference, Voltage Monitors, and Temp Sensor

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MAX1329 Datasheet, PDF (25/78 Pages) Maxim Integrated Products – 12-/16-Bit DASs with ADC, DACs, DPIOs, APIOs, Reference, Voltage Monitors, and Temp Sensor

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12-/16-Bit DASs with ADC, DACs, DPIOs, APIOs,

Reference, Voltage Monitors, and Temp Sensor

SCLK

DIN

DOUT

tCSH

tCYC

tCH

tCSS

tCL

tDS

tDH

tDV

tCSH

tDO

tTR

Figure 1. Detailed Serial-Interface Timing Diagram

Detailed Description

The MAX1329/MAX1330 smart DASs are based on a

312ksps, 12-bit SAR ADC with a 1ksps, 16-bit DSP

mode. The ADC includes a differential multiplexer, a pro-

grammable gain amplifier (PGA) with gains of 1, 2, 4,

and 8, a 20-bit accumulator, internal dither, a 16-word

FIFO, and an alarm register. The MAX1329/MAX1330

operate with a digital supply down to 1.8V and feature an

internal charge pump to boost the supply voltage for the

analog circuitry that requires 2.7V to 5.5V.

The MAX1329/MAX1330 include an internal reference

with programmable buffer for the ADC, two analog exter-

nal inputs as well as inputs from other internal circuitry,

an internal/external temperature sensor, internal oscilla-

tor, dual single-pole, double-throw (SPDT) switches, four

digital programmable I/Os, four analog programmable

I/Os, and dual programmable voltage monitors.

The MAX1329 features dual 12-bit force-sense DACs

with programmable reference buffer and one opera-

tional amplifier. The MAX1330 includes one 12-bit force-

sense DAC with programmable reference buffer and

dual op amps. DACA can be sequenced with a 16-word

FIFO. The DAC buffers and op amps have internal ana-

log switches between the output and the inverting input.

Power-On Reset

After a power-on reset, the DVDD voltage supervisor is

enabled with thresholds at 1.8V and 2.7V. All digital

and analog programmable I/Os (DPIOs and APIOs) are

configured as inputs with pullups enabled. The internal

oscillator is enabled and is output at CLKIO once the

1.8V reset trip threshold has been exceeded and the

subsequent timeout period has expired. See the

DOUT

3kâ¦

DVDD

3kâ¦

DOUT

CLOAD = 20pF

a) FOR ENABLE, HIGH IMPEDANCE

b) FOR ENABLE, HIGH IMPEDANCE

TO VOH AND VOL TO VOH.

TO VOL AND VOH TO VOL.

FOR DISABLE, VOH TO HIGH IMPEDANCE. FOR DISABLE, VOL TO HIGH IMPEDANCE.

Figure 2. DOUT Enable and Disable Time Load Circuits

after a power-on reset.

After applying power to AVDD:

Power-On Setup

1) Write to the Reset register. This initializes the tem-

perature sensor and voltage reference trim logic.

2) Within 3ms following the reset, configure the charge

pump as desired by writing to the CP/VM Control

pump are described in the Charge Pump section.

Charge Pump

Power AVDD and DVDD by any one of the following

ways: drive AVDD and DVDD with a single external

power supply, drive AVDD and DVDD with separate

external power supplies, or drive DVDD with an external

supply and enable the internal charge pump to gener-

ate AVDD or short DVDD to AVDD internally.

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