MAX1329 Datasheet, PDF (37/78 Pages) Maxim Integrated Products – 12-/16-Bit DASs with ADC, DACs, DPIOs, APIOs, Reference, Voltage Monitors, and Temp Sensor

12-/16-Bit DASs with ADC, DACs, DPIOs, APIOs,
Reference, Voltage Monitors, and Temp Sensor
Once configured, autoconvert mode initiates with one
ADC Convert command. Conversions continue at the
rate selected by the ADC Autoconvert bits (see Table 4)
until disabled by writing to the ADC Control register. The
Autoconvert mode can run only in the normal or fast
power-down modes. The autoconvert function must be
disabled to use burst mode or DPIO CONVST mode.
When writing to the ADC Control register in fast power-
down mode with autoconvert disabled, acquisition
begins on the 1st rising ADC clock edge after CS tran-
sitions high, and ends after the programmed number of
clock cycles. The conversion completes a minimum 14
clock cycles after acquisition ends. When autoconvert
is enabled, an additional three ADC clock cycles are
added prior to acquisition to allow the ADC to wake up.
See Figures 19 and 20 for timing diagrams.
CS
SCLK
12 345678
DIN
X 1 M3 M2 M1 M0 G1 G0 BIP
CLKIO
1 2 3 4 5 6 7 8 9 10 11 12 13 18 19
ADC MODE
TRACK
CONVERT
PD*
ADCDONE**
*PD IS AN INTERNAL SIGNAL. WHEN PD IS HIGH, THE ADC IS POWERED DOWN.
**ADCDONE IS AN INTERNAL SIGNAL. RISING EDGE ADCDONE SETS THE ADD BIT IN THE STATUS REGISTER.
X = DON'T CARE.
Figure 20. Write Command to Start ADC Normal or Fast Power-Down, with Autoconvert Enabled and Conversions Clocked by CLKIO
(OSCE = 0, ADDIV<1:0> = 00, CLKIO<1:0> = 11)
CLKIO
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
ADC MODE
TRACK
CONVERT
TRACK
CONVERT
DPIO (CONVST)
PD*
EDGE TRIGGERED
ADCDONE**
*PD IS AN INTERNAL SIGNAL. WHEN PD IS HIGH, THE ADC IS POWERED DOWN.
**ADCDONE IS AN INTERNAL SIGNAL. RISING EDGE ADCDONE SETS THE ADD BIT IN THE STATUS REGISTER.
ADDIV = 00.
Figure 21. DPIO-Controlled ADC Conversion Start
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