MAX1329 Datasheet, PDF (63/78 Pages) Maxim Integrated Products – 12-/16-Bit DASs with ADC, DACs, DPIOs, APIOs, Reference, Voltage Monitors, and Temp Sensor

12-/16-Bit DASs with ADC, DACs, DPIOs, APIOs,
Reference, Voltage Monitors, and Temp Sensor
POWER
SUPPLY
0.1µF
2.7V TO 3.6V
0.1µF
0.1µF
DV_DD C1A C1B AV_DD
RST1
MAX1329
MAX1330
RST2
DGND
AGND
V_DD
INTERRUPT
µC
RESET
DGND
POWER
SUPPLY
C_DVDD
2.7V TO 3.6V
C_FLY
5.0V
C_AVDD
0.1µF
DV_DD C1A C1B AV_DD
V_DD
RST1
MAX1329
MAX1330
RST2
INTERRUPT
µC
RESET
DGND
AGND
DGND
Figure 23. Power-Supply Circuit Using an External 3.0V Power
Supply for DV_DD and AV_DD
Applications Information
Power-Supply Considerations
The circuit in Figure 23 applies an external 3.0V power
supply to both DV_DD and AV_DD. To drive AV_DD directly,
disable the internal charge pump through the CP/VM
Control register. The bypass switch between DV_DD and
AV_DD can be either open or closed in this configuration.
Figure 24 shows the charge pump enabled to supply
AV_DD. The charge-pump output voltage is set to 5.0V
through the CP/VM Control register. See the Charge-
Pump Component Selection section.
Figure 25 shows DV_DD is powered from a battery with
the charge-pump output set to 3.0V. The charge pump
can draw high peak currents from DV_DD under maxi-
mum load. Select an appropriately sized bypass capac-
itor for DV_DD (≥ 10 times C_FLY). Supply ripple can be
reduced by increasing CA_VDD and/or the charge-pump
clock frequency.
Running Directly Off Batteries
The MAX1329/MAX1330 can be powered directly from
two alkaline cells, two silver oxide button cells, or a lithi-
um-coin cell. DV_DD requires 1.8V to 3.6V and AV_DD
requires 2.7V to 5.5V for proper operation. Save power
by running DV_DD directly off the battery and shorting to
AV_DD by closing the internal bypass switch. Use the
2.7V AV_DD voltage monitor to detect when it drops to
2.7V. Power is saved during this time because the inter-
nal charge pump is off. Once the battery voltage drops
to 2.7V, open the bypass switch and enable the internal
charge pump as long as DV_DD is between 1.8V and
2.7V. Following this procedure optimizes the battery life.
Figure 24. Power-Supply Circuit Using an External 3.0V Power
Supply for DV_DD and Internal Charge Pump Set to 5V for AV_DD
C_DVDD
E1
1.8V TO 3.6V
C_FLY
3.0V
C_AVDD
DV_DD C1A C1B AV_DD
0.1µF
V_DD
RST1
MAX1329
MAX1330
RST2
RESET
µC
INTERRUPT
DGND
AGND
DGND
Figure 25. Power-Supply Circuit Using a Battery for DV_DD and
Internal Charge Pump Set to 3.0V for AV_DD
Digital-Interface Connections
Figure 26 provides standard digital-interface connections
between the MAX1329/MAX1330 and a µC. The µC gen-
erates its own 32kHz clock for timekeeping and the
MAX1329/MAX1330 provide the high-frequency clock
required by the µC. See the Clock Control Register sec-
tion to program the CLKIO output and frequency and set
the ODLY bit to delay the turn-off time to enable the µC
time to go to sleep. During sleep, CLKIO becomes an
input and requires a weak pulldown resistor (≤1MΩ) to
minimize power dissipation. See the DPIO Setup and
DPIO Control registers to program DPIO1–DPIO4 as
wake-ups. Upon wake-up, the internal oscillator starts and
outputs to CLKIO. See the CP/VM Control Register sec-
tion to program the RST1 and RST2 as a reset or interrupt.
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