MAX1329 Datasheet, PDF (30/78 Pages) Maxim Integrated Products – 12-/16-Bit DASs with ADC, DACs, DPIOs, APIOs, Reference, Voltage Monitors, and Temp Sensor

12-/16-Bit DASs with ADC, DACs, DPIOs, APIOs,
Reference, Voltage Monitors, and Temp Sensor
FROM
SERIAL I/O
DAC INPUT
REGISTER
FROM
REFDAC
DAC OUTPUT
REGISTER
12-BIT
DAC
TO DAC
OUTPUT
BUFFER
FIFOA
CONTROL
REGISTER
16-WORD DAC
FIFO
DDS
LOGIC
FOR DACA ONLY
Figure 7. Detailed DAC and FIFO Block Diagram
determines the analog output voltage. An internal switch
configures the force-sense output for unity gain config-
uration when it is closed.
In power-down mode, the DAC outputs and feedback
inputs are high impedance.
DACA FIFO and Direct
Digital Synthesis (DDS) Logic
The DACA FIFO and DDS logic can be used for wave-
form synthesis by loading the FIFO and configuring the
DDS mode through the FIFOA Control register. The
FIFO is sequenced by writing to the FIFO Sequence
register address or by toggling a DPIO configured for
this function.
The input register value, in conjunction with the FIFOA
Data register values, can be used to create waveforms.
The FIFOA Data register values are added to or sub-
tracted from the Input register value before shifting to
the output register. The FIFO data is straight binary (0
to +4095) when the bipolar bit (BIPA) is not asserted
and as sign magnitude (-2047 to +2047) when BIPA is
asserted. In sign magnitude mode, the MSB represents
the sign bit, where 0 indicates a positive number and 1
indicates a negative number. The 11 LSBs provide the
magnitude in sign magnitude.
The type of waveform generated is determined by the
asymmetric/symmetric mode bit (SYMA), unipolar/bipo-
lar mode bit (BIPA), and the single/continuous mode bit
(CONA). All waveforms are generated in phases (see
Figure 8). For all bit combinations, phase 1 is created
by first shifting the input register value to the output reg-
16
12
8
4
PHASE 1 PHASE 2
DAC INPUT
0
REGISTER VALUE
PLUS FIFO
-4
LOCATION 1 VALUE
DAC INPUT
-8 REGISTER VALUE
DAC INPUT REGISTER
VALUE MINUS FIFO
LOCATION 1 VALUE
PHASE 3 PHASE 4
DAC INPUT REGISTER
-12
VALUE MINUS FIFO
LOCATION 16 VALUE
-16
0
16
32
48
64
SEQUENCE NUMBER
Figure 8. DAC FIFO Waveform Phases
ister. For each subsequent sequence, the FIFOA Data
register value is added to the input register before shift-
ing to the output register until the programmed FIFO
depth has been reached (see Figure 9a). The FIFO
depth (DPTA<3:0>) can be set to any integer value from
1 to 16 and the FIFO always starts at location 1.
Asserting the SYMA bit creates phase two by causing
the FIFO to reverse direction at the end of phase 1 with-
out repeating the final value before sequencing back to
the beginning (see Figure 9c).
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