MAX1329 Datasheet, PDF (45/78 Pages) Maxim Integrated Products – 12-/16-Bit DASs with ADC, DACs, DPIOs, APIOs, Reference, Voltage Monitors, and Temp Sensor

12-/16-Bit DASs with ADC, DACs, DPIOs, APIOs,
Reference, Voltage Monitors, and Temp Sensor
Read Format
A single read from the ADC FIFO register returns the
ADC FIFO data and the 4-bit FIFO address (AFFA<3:0>)
corresponding to the location read.
After clocking out the 16-bit word, the read pointer
increments and continual clock shifts out the 16-bit
word at the location pointed to by the ADC FIFO read
pointer. If trying to read from the ADC FIFO at a location
pointed to by the ADC FIFO write pointer, the FIFO
repeats the last ADC conversion result and correspond-
ing ADC FIFO address equivalent to the ADC FIFO
write pointer. To stop reading, bring CS high after
clocking out the 16th bit of a complete word. The read
pointer increments after each complete 16-bit word
read. It does not increment if the read is aborted by
bringing CS high before clocking out all 16 bits. Any
read operation on the ADC FIFO register resets the
interrupt flag (AFF).
AFFDATA<11:0>: ADC FIFO Read Data bits (default =
0000 0000 0000). AFFDATA<11:0> returns the data
written by the ADC at the current read pointer location.
AFFA<3:0>: ADC FIFO Read Address bits (default =
0000). AFFA<3:0> returns the address of the current
read pointer location. AFFA<3:0> is never greater than
the AFFD<3:0> programmed value.
NAME
DEFAULT
MSB
AFFDATA11 AFFDATA10
0
0
AFFDATA9
0
AFFDATA8
0
AFFDATA7
0
AFFDATA6
0
AFFDATA5
0
AFFDATA4
0
NAME
AFFDATA3 AFFDATA2 AFFDATA1 AFFDATA0
AFFA3
AFFA2
DEFAULT
0
0
0
0
0
0
Note: Data length can vary from 1 to 16 words, where a word is 16 bits (12 data bits plus 4 address bits).
AFFA1
0
LSB
AFFA0
0
Table 10. ADC FIFO Depth Bit
Configuration
ADC FIFO WRITE
AFFD3 AFFD2 AFFD1 AFFD0 WORD POINTER
DEPTH RANGE
0
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
1
0
0
0
1
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
FIFO disabled
2
0-1
3
0-2
4
0-3
5
0-4
6
0-5
7
0-6
8
0-7
9
0-8
10
0-9
11
0-10
12
0-11
13
0-12
14
0-13
15
0-14
16
0-15
Table 11. ADC FIFO Interrupt-Address Bit
Configuration
AFFI3 AFFI2 AFFI1 AFFI0
ADC FIFO
INTERRUPT
ADDRESS
0
0
0
0
0
0
0
0
1
1
0
0
1
0
2
0
0
1
1
3
0
1
0
0
4
0
1
0
1
5
0
1
1
0
6
0
1
1
1
7
1
0
0
0
8
1
0
0
1
9
1
0
1
0
10
1
0
1
1
11
1
1
0
0
12
1
1
0
1
13
1
1
1
0
14
1
1
1
1
15
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